Index: lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
===================================================================
--- lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
+++ lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
@@ -321,9 +321,11 @@
       if (I != MBB.end() && I->getOpcode() == AMDGPU::CF_ALU)
         continue; // BB was already parsed
       for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
-        if (isALU(*I))
-          I = MakeALUClause(MBB, I);
-        else
+        if (isALU(*I)) {
+          auto next = MakeALUClause(MBB, I);
+          assert(next != I);
+          I = next;
+        } else
           ++I;
       }
     }
Index: test/CodeGen/AMDGPU/r600.alu-limits.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/r600.alu-limits.ll
@@ -0,0 +1,33 @@
+; RUN: opt -loop-unroll -unroll-threshold=2000 -S < %s | llc -march=r600 -mcpu=cypress | FileCheck %s
+; XFAIL: *
+
+; CHECK: {{^}}@alu_limits:
+
+%struct.foo = type {i32, i32, i32}
+
+define void @alu_limits(i32 addrspace(1)* %out, %struct.foo* %in, i32 %offset) {
+entry:
+  %ptr = getelementptr inbounds %struct.foo, %struct.foo* %in, i32 1, i32 2
+  %x = load i32, i32 *%ptr, align 4
+  br label %loop
+loop:
+  %i = phi i32 [ 100, %entry ], [ %nexti, %loop ]
+  %val = phi i32 [ 1, %entry ], [ %nextval, %loop ]
+
+  %nexti = sub i32 %i, 1
+
+  %y = xor i32 %x, %i
+  %nextval = mul i32 %val, %y
+
+  %cond = icmp ne i32 %nexti, 0
+  br i1 %cond, label %loop, label %end
+end:
+  %out_val = add i32 %nextval, 4
+  store i32 %out_val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+!1 = !{!"omnipotent char", !2, i64 0}
+!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"float", !1, i64 0}
+!4 = !{!3, !3, i64 0}