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Tighten ARMConstantInslands pass for Thumb-1 targets

Authored by rmaprath on Feb 9 2017, 7:30 AM.



This pass takes blocks of the form:

%R0<def>, %CPSR<def,dead> = tLSLri %R0<kill>, 2
%R1<def> = tLEApcrelJT <jt#0>
%R0<def> = tLDRr %R0<kill>, %R1<kill>
tBR_JTr %R0<kill>, <jt#0>

And turns them into:

tTBB_JT %PC, %R0<kill>, <jt#0>, 0
JUMPTABLE_TBB 0, <jt#0>, <some-calculated-offset>

However, this assumes that R0 (index register) is not written to between
the tLDRr and the tBR_JTr instructions. This patch tightens the pass so
that when such an intervening instruction is present, the input block is
left un-altered.

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Event Timeline

rmaprath created this revision.Feb 9 2017, 7:30 AM
john.brawn added inline comments.Feb 10 2017, 9:39 AM

Please use spaces instead of tabs.

rmaprath updated this revision to Diff 88187.Feb 13 2017, 5:41 AM

Addressing review comments: Get rid of the tab characters.

rmaprath marked an inline comment as done.Feb 13 2017, 5:42 AM
rmaprath abandoned this revision.Feb 13 2017, 6:47 AM

Abandoning: @jmolloy has committed a semantically equivalent patch: