Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -72,8 +72,6 @@ def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", "HasHardwareDivideInARM", "true", "Enable divide instructions in ARM mode">; -def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", - "Enable Thumb2 extract and pack instructions">; def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", "Has data barrier (dmb / dsb) instructions">; def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", @@ -297,8 +295,7 @@ FeatureV7Clrex]>; def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", "Support ARM v8 instructions", - [HasV7Ops, FeatureAcquireRelease, - FeatureT2XtPk]>; + [HasV7Ops, FeatureAcquireRelease]>; def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", "Support ARM v8.1a instructions", [HasV8Ops]>; @@ -393,8 +390,7 @@ def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, - FeatureDSP, - FeatureT2XtPk]>; + FeatureDSP]>; def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; @@ -415,15 +411,13 @@ FeatureNEON, FeatureDB, FeatureDSP, - FeatureAClass, - FeatureT2XtPk]>; + FeatureAClass]>; def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, FeatureDB, FeatureDSP, FeatureHWDiv, - FeatureRClass, - FeatureT2XtPk]>; + FeatureRClass]>; def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, FeatureThumb2, @@ -438,8 +432,7 @@ FeatureDB, FeatureHWDiv, FeatureMClass, - FeatureDSP, - FeatureT2XtPk]>; + FeatureDSP]>; def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, FeatureAClass, @@ -483,7 +476,6 @@ FeatureDB, FeatureHWDiv, FeatureHWDivARM, - FeatureT2XtPk, FeatureDSP, FeatureCRC, FeatureMP, @@ -764,7 +756,6 @@ def : ProcNoItin<"cortex-m33", [ARMv8mMainline, FeatureDSP, - FeatureT2XtPk, FeatureFPARMv8, FeatureD16, FeatureVFPOnlySP]>; Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -10002,7 +10002,7 @@ (Mask == ~Mask2)) { // The pack halfword instruction works better for masks that fit it, // so use that when it's available. - if (Subtarget->hasT2ExtractPack() && + if (Subtarget->hasDSP() && (Mask == 0xffff || Mask == 0xffff0000)) return SDValue(); // 2a @@ -10018,7 +10018,7 @@ (~Mask == Mask2)) { // The pack halfword instruction works better for masks that fit it, // so use that when it's available. - if (Subtarget->hasT2ExtractPack() && + if (Subtarget->hasDSP() && (Mask2 == 0xffff || Mask2 == 0xffff0000)) return SDValue(); // 2b Index: lib/Target/ARM/ARMInstrFormats.td =================================================================== --- lib/Target/ARM/ARMInstrFormats.td +++ lib/Target/ARM/ARMInstrFormats.td @@ -1013,9 +1013,6 @@ class Thumb2DSPMulPat : Pat { list Predicates = [IsThumb2, UseMulOps, HasDSP]; } -class Thumb2ExtractPat : Pat { - list Predicates = [IsThumb2, HasT2ExtractPack]; -} //===----------------------------------------------------------------------===// // Thumb Instruction Format Definitions. // Index: lib/Target/ARM/ARMInstrInfo.td =================================================================== --- lib/Target/ARM/ARMInstrInfo.td +++ lib/Target/ARM/ARMInstrInfo.td @@ -247,9 +247,6 @@ AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; -def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, - AssemblerPredicate<"FeatureT2XtPk", - "pack/extract">; def HasDSP : Predicate<"Subtarget->hasDSP()">, AssemblerPredicate<"FeatureDSP", "dsp">; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, Index: lib/Target/ARM/ARMInstrThumb2.td =================================================================== --- lib/Target/ARM/ARMInstrThumb2.td +++ lib/Target/ARM/ARMInstrThumb2.td @@ -1121,28 +1121,10 @@ /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -class T2I_ext_rrot opcod, string opc, PatFrag opnode> - : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, - opc, ".w\t$Rd, $Rm$rot", - [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, - Requires<[IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - - bits<2> rot; - let Inst{5-4} = rot{1-0}; // rotate -} - -// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. -class T2I_ext_rrot_uxtb16 opcod, string opc, PatFrag opnode> - : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), - IIC_iEXTr, opc, "\t$Rd, $Rm$rot", - [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, - Requires<[HasT2ExtractPack, IsThumb2]> { +class T2I_ext_rrot_base opcod, dag iops, dag oops, + string opc, string oprs, + list pattern> + : T2TwoReg { bits<2> rot; let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; @@ -1150,46 +1132,31 @@ let Inst{19-16} = 0b1111; // Rn let Inst{15-12} = 0b1111; let Inst{7} = 1; - let Inst{5-4} = rot; + let Inst{5-4} = rot; // rotate } -// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern -// supported yet. -class T2I_ext_rrot_sxtb16 opcod, string opc> - : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, - opc, "\t$Rd, $Rm$rot", []>, - Requires<[IsThumb2, HasT2ExtractPack]> { - bits<2> rot; - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = rot; -} +class T2I_ext_rrot opcod, string opc> + : T2I_ext_rrot_base, + Requires<[IsThumb2]>; + +// UXTB16, SXTB16 - Requires T2ExtractPack, does not need the .w qualifier. +class T2I_ext_rrot_xtb16 opcod, string opc> + : T2I_ext_rrot_base, + Requires<[HasDSP, IsThumb2]>; /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -class T2I_exta_rrot opcod, string opc, PatFrag opnode> +class T2I_exta_rrot opcod, string opc> : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), - IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", - [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>, - Requires<[HasT2ExtractPack, IsThumb2]> { - bits<2> rot; - let Inst{31-27} = 0b11111; - let Inst{26-23} = 0b0100; - let Inst{22-20} = opcod; - let Inst{15-12} = 0b1111; - let Inst{7} = 1; - let Inst{5-4} = rot; -} - -class T2I_exta_rrot_np opcod, string opc> - : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>, - Requires<[HasT2ExtractPack, IsThumb2]> { + Requires<[HasDSP, IsThumb2]> { bits<2> rot; let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; @@ -1969,31 +1936,39 @@ // Sign extenders -def t2SXTB : T2I_ext_rrot<0b100, "sxtb", - UnOpFrag<(sext_inreg node:$Src, i8)>>; -def t2SXTH : T2I_ext_rrot<0b000, "sxth", - UnOpFrag<(sext_inreg node:$Src, i16)>>; -def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; +def t2SXTB : T2I_ext_rrot<0b100, "sxtb">; +def t2SXTH : T2I_ext_rrot<0b000, "sxth">; +def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">; + +def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">; +def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">; +def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">; + +def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8), + (t2SXTB rGPR:$Rn, rot_imm:$rot)>; +def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16), + (t2SXTH rGPR:$Rn, rot_imm:$rot)>; +def : Thumb2DSPPat<(add rGPR:$Rn, + (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)), + (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; +def : Thumb2DSPPat<(add rGPR:$Rn, + (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)), + (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; -def t2SXTAB : T2I_exta_rrot<0b100, "sxtab", - BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; -def t2SXTAH : T2I_exta_rrot<0b000, "sxtah", - BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; -def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; // A simple right-shift can also be used in most cases (the exception is the // SXTH operations with a rotate of 24: there the non-contiguous bits are // relevant). -def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg +def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; -def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg +def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16)), (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; -def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg +def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg (rotr rGPR:$Rm, (i32 24)), i16)), (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>; -def : Thumb2ExtractPat<(add rGPR:$Rn, (sext_inreg +def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg (or (srl rGPR:$Rm, (i32 24)), (shl rGPR:$Rm, (i32 8))), i16)), (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>; @@ -2001,12 +1976,16 @@ // Zero extenders let AddedComplexity = 16 in { -def t2UXTB : T2I_ext_rrot<0b101, "uxtb", - UnOpFrag<(and node:$Src, 0x000000FF)>>; -def t2UXTH : T2I_ext_rrot<0b001, "uxth", - UnOpFrag<(and node:$Src, 0x0000FFFF)>>; -def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", - UnOpFrag<(and node:$Src, 0x00FF00FF)>>; +def t2UXTB : T2I_ext_rrot<0b101, "uxtb">; +def t2UXTH : T2I_ext_rrot<0b001, "uxth">; +def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">; + +def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF), + (t2UXTB rGPR:$Rm, rot_imm:$rot)>; +def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF), + (t2UXTH rGPR:$Rm, rot_imm:$rot)>; +def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF), + (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>; // FIXME: This pattern incorrectly assumes the shl operator is a rotate. // The transformation should probably be done as a combiner action @@ -2017,18 +1996,22 @@ // Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), (t2UXTB16 rGPR:$Src, 1)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; -def t2UXTAB : T2I_exta_rrot<0b101, "uxtab", - BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; -def t2UXTAH : T2I_exta_rrot<0b001, "uxtah", - BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; -def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; +def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">; +def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">; +def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">; -def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), +def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), + 0x00FF)), + (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; +def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), + 0xFFFF)), + (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; +def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; -def : Thumb2ExtractPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), +def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; } @@ -2819,7 +2802,7 @@ [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 0xFFFF0000)))]>, - Requires<[HasT2ExtractPack, IsThumb2]>, + Requires<[HasDSP, IsThumb2]>, Sched<[WriteALUsi, ReadALU]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -2835,10 +2818,10 @@ // Alternate cases for PKHBT where identities eliminate some nodes. def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. @@ -2848,7 +2831,7 @@ [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 0xFFFF)))]>, - Requires<[HasT2ExtractPack, IsThumb2]>, + Requires<[HasDSP, IsThumb2]>, Sched<[WriteALUsi, ReadALU]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -2867,14 +2850,14 @@ // pkhtb src1, src2, asr (17..31). def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)), (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)), (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; //===----------------------------------------------------------------------===// // CRC32 Instructions @@ -4216,13 +4199,13 @@ def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, Requires<[IsThumb2]>; def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; } def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, @@ -4231,10 +4214,10 @@ Requires<[IsThumb2]>; def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; // Atomic load/store patterns def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), @@ -4431,10 +4414,10 @@ // input operands swapped when the shift amount is zero (i.e., unspecified). def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; // PUSH/POP aliases for STM/LDM def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; @@ -4513,16 +4496,16 @@ // Extend instruction optional rotate operand. def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm", (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm", (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"sxtb16${p} $Rd, $Rm", (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : t2InstAlias<"sxtb${p} $Rd, $Rm", (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; @@ -4535,16 +4518,16 @@ def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm", (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm", (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : InstAlias<"uxtb16${p} $Rd, $Rm", (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : t2InstAlias<"uxtb${p} $Rd, $Rm", (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; @@ -4560,7 +4543,7 @@ (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; def : InstAlias<"uxtb16${p} $Rd, $Rm$rot", (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : t2InstAlias<"uxth${p} $Rd, $Rm$rot", (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; @@ -4568,7 +4551,7 @@ (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; def : InstAlias<"sxtb16${p} $Rd, $Rm$rot", (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>, - Requires<[HasT2ExtractPack, IsThumb2]>; + Requires<[HasDSP, IsThumb2]>; def : t2InstAlias<"sxth${p} $Rd, $Rm$rot", (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; Index: lib/Target/ARM/ARMSubtarget.h =================================================================== --- lib/Target/ARM/ARMSubtarget.h +++ lib/Target/ARM/ARMSubtarget.h @@ -166,10 +166,6 @@ /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode bool HasHardwareDivideInARM = false; - /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack - /// instructions. - bool HasT2ExtractPack = false; - /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier /// instructions. bool HasDataBarrier = false; @@ -461,7 +457,6 @@ bool hasDivide() const { return HasHardwareDivide; } bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } - bool hasT2ExtractPack() const { return HasT2ExtractPack; } bool hasDataBarrier() const { return HasDataBarrier; } bool hasV7Clrex() const { return HasV7Clrex; } bool hasAcquireRelease() const { return HasAcquireRelease; } Index: test/CodeGen/Thumb2/thumb2-sxt-uxt.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-sxt-uxt.ll +++ test/CodeGen/Thumb2/thumb2-sxt-uxt.ll @@ -1,5 +1,8 @@ ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m4 %s -o - | FileCheck %s --check-prefix=CHECK-M4 +; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv7EM +; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M +; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M-DSP define i32 @test1(i16 zeroext %z) nounwind { ; CHECK-LABEL: test1: @@ -33,6 +36,9 @@ ; CHECK-LABEL: test5: ; CHECK-NOT: sxtab ; CHECK-M4: sxtab r0, r0, r1 +; CHECK-ARMv7EM: sxtab r0, r0, r1 +; CHECK-ARMv8M-DSP: sxtab r0, r0, r1 +; CHECK-ARMv8M-NOT: sxtab r0, r0, r1 %sext = sext i8 %b to i32 %add = add i32 %a, %sext ret i32 %add @@ -42,6 +48,9 @@ ; CHECK-LABEL: test6: ; CHECK-NOT: sxtab ; CHECK-M4: sxtab r0, r0, r1 +; CHECK-ARMv7EM: sxtab r0, r0, r1 +; CHECK-ARMv8M-DSP: sxtab r0, r0, r1 +; CHECK-ARMv8M-NOT: sxtab r0, r0, r1 %shl = shl i32 %b, 24 %ashr = ashr i32 %shl, 24 %add = add i32 %a, %ashr @@ -52,6 +61,9 @@ ; CHECK-LABEL: test7: ; CHECK-NOT: sxtah ; CHECK-M4: sxtah r0, r0, r1 +; CHECK-ARMv7EM: sxtah r0, r0, r1 +; CHECK-ARMv8M-DSP: sxtah r0, r0, r1 +; CHECK-ARMv8M-NOT: sxtah r0, r0, r1 %sext = sext i16 %b to i32 %add = add i32 %a, %sext ret i32 %add @@ -61,6 +73,9 @@ ; CHECK-LABEL: test8: ; CHECK-NOT: sxtah ; CHECK-M4: sxtah r0, r0, r1 +; CHECK-ARMv7EM: sxtah r0, r0, r1 +; CHECK-ARMv8M-DSP: sxtah r0, r0, r1 +; CHECK-ARMv8M-NOT: sxtah r0, r0, r1 %shl = shl i32 %b, 16 %ashr = ashr i32 %shl, 16 %add = add i32 %a, %ashr @@ -71,6 +86,9 @@ ; CHECK-LABEL: test9: ; CHECK-NOT: uxtab ; CHECK-M4: uxtab r0, r0, r1 +; CHECK-ARMv7EM: uxtab r0, r0, r1 +; CHECK-ARMv8M-DSP: uxtab r0, r0, r1 +; CHECK-ARMv8M-NOT: uxtab r0, r0, r1 %zext = zext i8 %b to i32 %add = add i32 %a, %zext ret i32 %add @@ -80,6 +98,9 @@ ;CHECK-LABEL: test10: ;CHECK-NOT: uxtab ;CHECK-M4: uxtab r0, r0, r1 +;CHECK-ARMv7EM: uxtab r0, r0, r1 +;CHECK-ARMv8M-DSP: uxtab r0, r0, r1 +;CHECK-ARMv8M-NOT: uxtab r0, r0, r1 %and = and i32 %b, 255 %add = add i32 %a, %and ret i32 %add @@ -89,6 +110,9 @@ ; CHECK-LABEL: test11: ; CHECK-NOT: uxtah ; CHECK-M4: uxtah r0, r0, r1 +; CHECK-ARMv7EM: uxtah r0, r0, r1 +; CHECK-ARMv8M-DSP: uxtah r0, r0, r1 +; CHECK-ARMv8M-NOT: uxtah r0, r0, r1 %zext = zext i16 %b to i32 %add = add i32 %a, %zext ret i32 %add @@ -98,6 +122,9 @@ ;CHECK-LABEL: test12: ;CHECK-NOT: uxtah ;CHECK-M4: uxtah r0, r0, r1 +;CHECK-ARMv7EM: uxtah r0, r0, r1 +;CHECK-ARMv8M-DSP: uxtah r0, r0, r1 +;CHECK-ARMv8M-NOT: uxtah r0, r0, r1 %and = and i32 %b, 65535 %add = add i32 %a, %and ret i32 %add Index: test/CodeGen/Thumb2/thumb2-sxt_rot.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-sxt_rot.ll +++ test/CodeGen/Thumb2/thumb2-sxt_rot.ll @@ -1,10 +1,16 @@ -; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2,+t2xtpk %s -o - | FileCheck %s +; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-M3 +; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv7EM +; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M +; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-ARMv8M-DSP define i32 @test0(i8 %A) { ; CHECK-LABEL: test0: ; CHECK: sxtb r0, r0 ; CHECK-M3: sxtb r0, r0 +; CHECK-ARMv7EM: sxtb r0, r0 +; CHECK-ARMv8M: sxtb r0, r0 +; CHECK-ARMv8M-DSP: sxtb r0, r0 %B = sext i8 %A to i32 ret i32 %B } @@ -13,6 +19,9 @@ ; CHECK-LABEL: test1: ; CHECK: sbfx r0, r0, #8, #8 ; CHECK-M3: sbfx r0, r0, #8, #8 +; CHECK-ARMv7M: sbfx r0, r0, #8, #8 +; CHECK-ARMv8M: sbfx r0, r0, #8, #8 +; CHECK-ARMv8M-DSP: sbfx r0, r0, #8, #8 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C @@ -23,7 +32,10 @@ define signext i32 @test2(i32 %A, i32 %X) { ; CHECK-LABEL: test2: ; CHECK: sxtab r0, r1, r0, ror #8 +; CHECK-ARMv7EM: sxtab r0, r1, r0, ror #8 +; CHECK-ARMv8M-DSP: sxtab r0, r1, r0, ror #8 ; CHECK-M3-NOT: sxtab +; CHECK-ARMv8M-NOT: sxtab %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C @@ -36,7 +48,10 @@ define i32 @test3(i32 %A, i32 %X) { ; CHECK-LABEL: test3: ; CHECK: sxtah r0, r0, r1, ror #8 +; CHECK-ARMv7EM: sxtah r0, r0, r1, ror #8 +; CHECK-ARMv8M-DSP: sxtah r0, r0, r1, ror #8 ; CHECK-M3-NOT: sxtah +; CHECK-ARMv8M-NOT: sxtah %X.hi = lshr i32 %X, 8 %X.trunc = trunc i32 %X.hi to i16 %addend = sext i16 %X.trunc to i32 @@ -47,7 +62,10 @@ define signext i32 @test4(i32 %A, i32 %X) { ; CHECK-LABEL: test4: ; CHECK: sxtab r0, r1, r0, ror #16 +; CHECK-ARMv7EM: sxtab r0, r1, r0, ror #16 +; CHECK-ARMv8M-DSP: sxtab r0, r1, r0, ror #16 ; CHECK-M3-NOT: sxtab +; CHECK-ARMv8M-NOT: sxtab %B = lshr i32 %A, 16 %C = shl i32 %A, 16 %D = or i32 %B, %C @@ -60,7 +78,10 @@ define signext i32 @test5(i32 %A, i32 %X) { ; CHECK-LABEL: test5: ; CHECK: sxtah r0, r1, r0, ror #24 +; CHECK-ARMv7EM: sxtah r0, r1, r0, ror #24 +; CHECK-ARMv8M-DSP: sxtah r0, r1, r0, ror #24 ; CHECK-M3-NOT: sxtah +; CHECK-ARMv8M-NOT: sxtah %B = lshr i32 %A, 24 %C = shl i32 %A, 8 %D = or i32 %B, %C Index: test/CodeGen/Thumb2/thumb2-uxt_rot.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-uxt_rot.ll +++ test/CodeGen/Thumb2/thumb2-uxt_rot.ll @@ -1,10 +1,16 @@ ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=A8 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=M3 +; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=ARMv7EM +; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=ARMv8M +; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=ARMv8M-DSP ; rdar://11318438 define zeroext i8 @test1(i32 %A.u) { ; CHECK-LABEL: test1: ; A8: uxtb r0, r0 +; ARMv7EM: uxtb r0, r0 +; ARMv8M: uxtb r0, r0 +; ARMv8M-DSP: uxtb r0, r0 %B.u = trunc i32 %A.u to i8 ret i8 %B.u } @@ -12,10 +18,16 @@ define zeroext i32 @test2(i32 %A.u, i32 %B.u) { ; CHECK-LABEL: test2: ; A8: uxtab r0, r0, r1 +; ARMv7EM: uxtab r0, r0, r1 +; ARMv8M-DSP: uxtab r0, r0, r1 ; M3: uxtb r1, r1 ; M3-NOT: uxtab ; M3: add r0, r1 + +; ARMv8M: uxtb r1, r1 +; ARMv8M-NOT: uxtab r0, r0, r1 +; ARMv8M: add r0, r1 %C.u = trunc i32 %B.u to i8 %D.u = zext i8 %C.u to i32 %E.u = add i32 %A.u, %D.u @@ -26,6 +38,9 @@ ; CHECK-LABEL: test3: ; A8: ubfx r0, r0, #8, #16 ; M3: ubfx r0, r0, #8, #16 +; ARMv7EM: ubfx r0, r0, #8, #16 +; ARMv8M: ubfx r0, r0, #8, #16 +; ARMv8M-DSP: ubfx r0, r0, #8, #16 %B.u = lshr i32 %A.u, 8 %C.u = shl i32 %A.u, 24 %D.u = or i32 %B.u, %C.u @@ -37,7 +52,10 @@ define i32 @test4(i32 %A, i32 %X) { ; CHECK-LABEL: test4: ; A8: uxtab r0, r0, r1, ror #16 +; ARMv7EM: uxtab r0, r0, r1, ror #16 +; ARMv8M-DSP: uxtab r0, r0, r1, ror #16 ; M3-NOT: uxtab +; ARMv8M-NOT: uxtab %X.hi = lshr i32 %X, 16 %X.trunc = trunc i32 %X.hi to i8 %addend = zext i8 %X.trunc to i32 @@ -48,7 +66,10 @@ define i32 @test5(i32 %A, i32 %X) { ; CHECK-LABEL: test5: ; A8: uxtah r0, r0, r1, ror #8 +; ARMv7EM: uxtah r0, r0, r1, ror #8 +; ARMv8M-DSP: uxtah r0, r0, r1, ror #8 ; M3-NOT: uxtah +; ARMv8M-NOT: uxtah %X.hi = lshr i32 %X, 8 %X.trunc = trunc i32 %X.hi to i16 %addend = zext i16 %X.trunc to i32 @@ -59,7 +80,10 @@ define i32 @test6(i32 %A, i32 %X) { ; CHECK-LABEL: test6: ; A8: uxtab r0, r0, r1, ror #8 +; ARMv7EM: uxtab r0, r0, r1, ror #8 +; ARMv8M-DSP: uxtab r0, r0, r1, ror #8 ; M3-NOT: uxtab +; ARMv8M-NOT: uxtab %X.hi = lshr i32 %X, 8 %X.trunc = trunc i32 %X.hi to i8 %addend = zext i8 %X.trunc to i32 @@ -70,7 +94,10 @@ define i32 @test7(i32 %A, i32 %X) { ; CHECK-LABEL: test7: ; A8: uxtah r0, r0, r1, ror #24 +; ARMv7EM: uxtah r0, r0, r1, ror #24 +; ARMv8M-DSP: uxtah r0, r0, r1, ror #24 ; M3-NOT: uxtah +; ARMv8M-NOT: uxtah %lshr = lshr i32 %X, 24 %shl = shl i32 %X, 8 %or = or i32 %lshr, %shl @@ -83,7 +110,10 @@ define i32 @test8(i32 %A, i32 %X) { ; CHECK-LABEL: test8: ; A8: uxtah r0, r0, r1, ror #24 +; ARMv7EM: uxtah r0, r0, r1, ror #24 +; ARMv8M-DSP: uxtah r0, r0, r1, ror #24 ; M3-NOT: uxtah +; ARMv8M-NOT: uxtah %lshr = lshr i32 %X, 24 %shl = shl i32 %X, 8 %or = or i32 %lshr, %shl Index: test/CodeGen/Thumb2/thumb2-uxtb.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-uxtb.ll +++ test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -1,72 +1,81 @@ ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=ARMv7A ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=ARMv7M +; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=ARMv7EM +; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=ARMv8M +; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=ARMv8M-DSP define i32 @test1(i32 %x) { -; ARMv7A: test1 +; CHECK-LABEL: test1 ; ARMv7A: uxtb16 r0, r0 - -; ARMv7M: test1 ; ARMv7M: bic r0, r0, #-16711936 +; ARMv7EM: uxtb16 r0, r0 +; ARMv8M-NOT: uxtb16 r0, r0 +; ARMv8M-DSP: uxtb16 r0, r0 %tmp1 = and i32 %x, 16711935 ; [#uses=1] ret i32 %tmp1 } ; PR7503 define i32 @test2(i32 %x) { -; ARMv7A: test2 +; CHECK-LABEL: test2 ; ARMv7A: uxtb16 r0, r0, ror #8 - -; ARMv7M: test2 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, lsr #8 +; ARMv7EM: uxtb16 r0, r0, ror #8 +; ARMv8M-NOT: uxtb16 +; ARMv8M-DSP: uxtb16 r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp2 } define i32 @test3(i32 %x) { -; ARMv7A: test3 +; CHECK-LABEL: test3 ; ARMv7A: uxtb16 r0, r0, ror #8 - -; ARMv7M: test3 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, lsr #8 +; ARMv7EM: uxtb16 r0, r0, ror #8 +; ARMv8M-NOT: uxtb16 r0, r0, ror #8 +; ARMv8M-DSP: uxtb16 r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp2 } define i32 @test4(i32 %x) { -; ARMv7A: test4 +; CHECK-LABEL: test4 ; ARMv7A: uxtb16 r0, r0, ror #8 - -; ARMv7M: test4 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, lsr #8 +; ARMv7EM: uxtb16 r0, r0, ror #8 +; ARMv8M-NOT: uxtb16 r0, r0, ror #8 +; ARMv8M-DSP: uxtb16 r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp6 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp6 } define i32 @test5(i32 %x) { -; ARMv7A: test5 +; CHECK-LABEL: test5 ; ARMv7A: uxtb16 r0, r0, ror #8 - -; ARMv7M: test5 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, lsr #8 +; ARMv7EM: uxtb16 r0, r0, ror #8 +; ARMv8M-NOT: uxtb16 r0, r0, ror #8 +; ARMv8M-DSP: uxtb16 r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; [#uses=1] ret i32 %tmp2 } define i32 @test6(i32 %x) { -; ARMv7A: test6 +; CHECK-LABEL: test6 ; ARMv7A: uxtb16 r0, r0, ror #16 - -; ARMv7M: test6 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, ror #16 +; ARMv7EM: uxtb16 r0, r0, ror #16 +; ARMv8M-NOT: uxtb16 r0, r0, ror #16 +; ARMv8M-DSP: uxtb16 r0, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; [#uses=1] %tmp2 = and i32 %tmp1, 255 ; [#uses=1] %tmp4 = shl i32 %x, 16 ; [#uses=1] @@ -76,12 +85,13 @@ } define i32 @test7(i32 %x) { -; ARMv7A: test7 +; CHECK-LABEL: test7 ; ARMv7A: uxtb16 r0, r0, ror #16 - -; ARMv7M: test7 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, ror #16 +; ARMv7EM: uxtb16 r0, r0, ror #16 +; ARMv8M-NOT: uxtb16 r0, r0, ror #16 +; ARMv8M-DSP: uxtb16 r0, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; [#uses=1] %tmp2 = and i32 %tmp1, 255 ; [#uses=1] %tmp4 = shl i32 %x, 16 ; [#uses=1] @@ -91,12 +101,13 @@ } define i32 @test8(i32 %x) { -; ARMv7A: test8 +; CHECK-LABEL: test8 ; ARMv7A: uxtb16 r0, r0, ror #24 - -; ARMv7M: test8 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, ror #24 +; ARMv7EM: uxtb16 r0, r0, ror #24 +; ARMv8M-NOT: uxtb16 r0, r0, ror #24 +; ARMv8M-DSP: uxtb16 r0, r0, ror #24 %tmp1 = shl i32 %x, 8 ; [#uses=1] %tmp2 = and i32 %tmp1, 16711680 ; [#uses=1] %tmp5 = lshr i32 %x, 24 ; [#uses=1] @@ -105,12 +116,13 @@ } define i32 @test9(i32 %x) { -; ARMv7A: test9 +; CHECK-LABEL: test9 ; ARMv7A: uxtb16 r0, r0, ror #24 - -; ARMv7M: test9 ; ARMv7M: mov.w r1, #16711935 ; ARMv7M: and.w r0, r1, r0, ror #24 +; ARMv7EM: uxtb16 r0, r0, ror #24 +; ARMv8M-NOT: uxtb16 r0, r0, ror #24 +; ARMv8M-DSP: uxtb16 r0, r0, ror #24 %tmp1 = lshr i32 %x, 24 ; [#uses=1] %tmp4 = shl i32 %x, 8 ; [#uses=1] %tmp5 = and i32 %tmp4, 16711680 ; [#uses=1] @@ -119,14 +131,13 @@ } define i32 @test10(i32 %p0) { -; ARMv7A: test10 +; CHECK-LABEL: test10 ; ARMv7A: mov.w r1, #16253176 ; ARMv7A: and.w r0, r1, r0, lsr #7 ; ARMv7A: lsrs r1, r0, #5 ; ARMv7A: uxtb16 r1, r1 ; ARMv7A: orrs r0, r1 -; ARMv7M: test10 ; ARMv7M: mov.w r1, #16253176 ; ARMv7M: and.w r0, r1, r0, lsr #7 ; ARMv7M: mov.w r1, #458759