Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7866,6 +7866,19 @@
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
 
+  // (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
+  // When the adde's carry is not used.
+  if (N0.getOpcode() == ISD::ADDE &&
+      N0.hasOneUse() &&
+      !N0.getNode()->hasAnyUseOfValue(1) &&
+      TLI.isOperationLegalOrCustom(ISD::ADDE, VT)) {
+    auto SL = SDLoc(N);
+    auto C1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
+    auto C2 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
+    return DAG.getNode(ISD::ADDE, SL, DAG.getVTList(VT, MVT::Glue),
+                       C1, C2, N0.getOperand(2));
+  }
+
   return SDValue();
 }
 
Index: test/CodeGen/X86/adde-carry.ll
===================================================================
--- test/CodeGen/X86/adde-carry.ll
+++ test/CodeGen/X86/adde-carry.ll
@@ -105,9 +105,9 @@
 ; CHECK-NEXT:    adcq $0, %rdx
 ; CHECK-NEXT:    movq %rax, (%rdi)
 ; CHECK-NEXT:    addq 8(%rdi), %rdx
-; CHECK-NEXT:    sbbq %rax, %rax
-; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    sbbl %eax, %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    addl %eax, 16(%rdi)
 ; CHECK-NEXT:    retq
 entry: