Index: llvm/trunk/include/llvm/ADT/Triple.h =================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h +++ llvm/trunk/include/llvm/ADT/Triple.h @@ -110,6 +110,7 @@ ARMSubArch_v7m, ARMSubArch_v7s, ARMSubArch_v7k, + ARMSubArch_v7ve, ARMSubArch_v6, ARMSubArch_v6m, ARMSubArch_v6k, Index: llvm/trunk/include/llvm/Support/ARMTargetParser.def =================================================================== --- llvm/trunk/include/llvm/Support/ARMTargetParser.def +++ llvm/trunk/include/llvm/Support/ARMTargetParser.def @@ -76,6 +76,9 @@ FK_NONE, ARM::AEK_NONE) ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7, FK_NEON, ARM::AEK_DSP) +ARM_ARCH("armv7ve", AK_ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7, + FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | + ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP)) ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7, FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP)) ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7, Index: llvm/trunk/lib/Support/TargetParser.cpp =================================================================== --- llvm/trunk/lib/Support/TargetParser.cpp +++ llvm/trunk/lib/Support/TargetParser.cpp @@ -725,6 +725,7 @@ case ARM::AK_ARMV8R: return ARM::PK_R; case ARM::AK_ARMV7A: + case ARM::AK_ARMV7VE: case ARM::AK_ARMV7K: case ARM::AK_ARMV8A: case ARM::AK_ARMV8_1A: @@ -761,6 +762,7 @@ case ARM::AK_ARMV6M: return 6; case ARM::AK_ARMV7A: + case ARM::AK_ARMV7VE: case ARM::AK_ARMV7R: case ARM::AK_ARMV7M: case ARM::AK_ARMV7S: Index: llvm/trunk/lib/Support/Triple.cpp =================================================================== --- llvm/trunk/lib/Support/Triple.cpp +++ llvm/trunk/lib/Support/Triple.cpp @@ -551,6 +551,8 @@ case ARM::AK_ARMV7A: case ARM::AK_ARMV7R: return Triple::ARMSubArch_v7; + case ARM::AK_ARMV7VE: + return Triple::ARMSubArch_v7ve; case ARM::AK_ARMV7K: return Triple::ARMSubArch_v7k; case ARM::AK_ARMV7M: Index: llvm/trunk/lib/Target/ARM/ARM.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td +++ llvm/trunk/lib/Target/ARM/ARM.td @@ -418,6 +418,16 @@ FeatureAClass, FeatureT2XtPk]>; +def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, + FeatureNEON, + FeatureDB, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureAClass, + FeatureT2XtPk]>; + def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, FeatureDB, FeatureDSP, @@ -481,8 +491,6 @@ def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, - FeatureHWDiv, - FeatureHWDivARM, FeatureT2XtPk, FeatureDSP, FeatureCRC, @@ -603,8 +611,6 @@ FeatureVMLxForwarding, FeatureMP, FeatureVFP4, - FeatureHWDiv, - FeatureHWDivARM, FeatureVirtualization]>; def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, @@ -636,8 +642,6 @@ FeatureTrustZone, FeatureVMLxForwarding, FeatureVFP4, - FeatureHWDiv, - FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureVirtualization, FeatureMP]>; @@ -651,8 +655,6 @@ FeatureVFP4, FeatureMP, FeatureCheckVLDnAlign, - FeatureHWDiv, - FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureVirtualization]>; @@ -663,8 +665,6 @@ FeatureMP, FeatureVMLxForwarding, FeatureVFP4, - FeatureHWDiv, - FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureVirtualization]>; Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.h =================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h @@ -51,9 +51,9 @@ }; enum ARMArchEnum { ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te, - ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r, - ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline, - ARMv8r + ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7ve, + ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, + ARMv8mBaseline, ARMv8r }; public: Index: llvm/trunk/test/CodeGen/ARM/build-attributes.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/build-attributes.ll +++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll @@ -186,6 +186,8 @@ ; ARMv7a ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; ARMv7ve +; RUN: llc < %s -mtriple=armv7ve-none-linux-gnueabi | FileCheck %s --check-prefix=V7VE ; ARMv7r ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN @@ -379,6 +381,22 @@ ; V7-FAST-NOT: .eabi_attribute 22 ; V7-FAST: .eabi_attribute 23, 1 +; V7VE: .syntax unified +; V7VE: .eabi_attribute 6, 10 @ Tag_CPU_arch +; V7VE: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile +; V7VE: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use +; V7VE: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use +; V7VE: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use +; V7VE: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal +; V7VE: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions +; V7VE: .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model +; V7VE: .eabi_attribute 24, 1 @ Tag_ABI_align_needed +; V7VE: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved +; V7VE: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format +; V7VE: .eabi_attribute 42, 1 @ Tag_MPextension_use +; V7VE: .eabi_attribute 44, 2 @ Tag_DIV_use +; V7VE: .eabi_attribute 68, 3 @ Tag_Virtualization_use + ; V8: .syntax unified ; V8: .eabi_attribute 67, "2.09" ; V8: .eabi_attribute 6, 14 Index: llvm/trunk/test/CodeGen/ARM/div.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/div.ll +++ llvm/trunk/test/CodeGen/ARM/div.ll @@ -10,12 +10,18 @@ ; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 | \ ; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=armv7ve-none-linux-gnu | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=thumbv7ve-none-linux-gnu | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV \ +; RUN: -check-prefix=CHECK-THUMB define i32 @f1(i32 %a, i32 %b) { entry: ; CHECK-LABEL: f1 ; CHECK-SWDIV: __divsi3 +; CHECK-THUMB: .thumb_func ; CHECK-HWDIV: sdiv ; CHECK-EABI: __aeabi_idiv @@ -28,6 +34,7 @@ ; CHECK-LABEL: f2 ; CHECK-SWDIV: __udivsi3 +; CHECK-THUMB: .thumb_func ; CHECK-HWDIV: udiv ; CHECK-EABI: __aeabi_uidiv @@ -40,6 +47,7 @@ ; CHECK-LABEL: f3 ; CHECK-SWDIV: __modsi3 +; CHECK-THUMB: .thumb_func ; CHECK-HWDIV: sdiv ; CHECK-HWDIV: mls @@ -55,6 +63,7 @@ ; CHECK-LABEL: f4 ; CHECK-SWDIV: __umodsi3 +; CHECK-THUMB: .thumb_func ; CHECK-HWDIV: udiv ; CHECK-HWDIV: mls Index: llvm/trunk/unittests/Support/TargetParserTest.cpp =================================================================== --- llvm/trunk/unittests/Support/TargetParserTest.cpp +++ llvm/trunk/unittests/Support/TargetParserTest.cpp @@ -17,17 +17,17 @@ namespace { const char *ARMArch[] = { - "armv2", "armv2a", "armv3", "armv3m", "armv4", - "armv4t", "armv5", "armv5t", "armv5e", "armv5te", - "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", - "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", - "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", - "armv7a", "armv7hl", "armv7l", "armv7-r", "armv7r", - "armv7-m", "armv7m", "armv7k", "armv7s", "armv7e-m", - "armv7em", "armv8-a", "armv8", "armv8a", "armv8.1-a", - "armv8.1a", "armv8.2-a", "armv8.2a", "armv8-r", "armv8r", - "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", - "iwmmxt2", "xscale"}; + "armv2", "armv2a", "armv3", "armv3m", "armv4", + "armv4t", "armv5", "armv5t", "armv5e", "armv5te", + "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", + "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", + "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", + "armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r", + "armv7r", "armv7-m", "armv7m", "armv7k", "armv7s", + "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a", + "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8-r", + "armv8r", "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", + "iwmmxt", "iwmmxt2", "xscale"}; bool testARMCPU(StringRef CPUName, StringRef ExpectedArch, StringRef ExpectedFPU, unsigned ExpectedFlags, @@ -315,6 +315,9 @@ testARMArch("armv7-a", "cortex-a8", "v7", ARMBuildAttrs::CPUArch::v7)); EXPECT_TRUE( + testARMArch("armv7ve", "generic", "v7ve", + ARMBuildAttrs::CPUArch::v7)); + EXPECT_TRUE( testARMArch("armv7-r", "cortex-r4", "v7r", ARMBuildAttrs::CPUArch::v7)); EXPECT_TRUE( @@ -502,12 +505,12 @@ TEST(TargetParserTest, ARMparseArchEndianAndISA) { const char *Arch[] = { - "v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t", - "v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2", - "v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a", - "v7", "v7a", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m", - "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v8.1-a", - "v8.1a", "v8.2-a", "v8.2a", "v8-r"}; + "v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t", + "v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2", + "v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a", + "v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m", + "v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", + "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8-r"}; for (unsigned i = 0; i < array_lengthof(Arch); i++) { std::string arm_1 = "armeb" + (std::string)(Arch[i]); @@ -559,6 +562,7 @@ EXPECT_EQ(ARM::PK_R, ARM::parseArchProfile(ARMArch[i])); continue; case ARM::AK_ARMV7A: + case ARM::AK_ARMV7VE: case ARM::AK_ARMV7K: case ARM::AK_ARMV8A: case ARM::AK_ARMV8_1A: