Expansion of the pseudo instruction EH_SjLj_LongJmp64 resulted in the LD instruction receiving a G8RC class register as opposed to the expected G8RC_NOX0 register.
Definition of MIoperandInfo for memr is ptr_rc. From what I can tell memr is used with:
LXVL/LXVLL vector loads
STXVL/STXVLL vector stores
Based on the ISA, the vector instructions and the LD/LWZ, that the SjLj pseudo-instructions translates to, all require G8RC_NO0X class registers for RA.