[PowerPC] pseudo instruction EH_SjLj_LongJmp64 requires G8RC_NOX0 register

[lei]

Summary

Expansion of the pseudo instruction EH_SjLj_LongJmp64 resulted in the LD instruction receiving a G8RC class register as opposed to the expected G8RC_NOX0 register.

Definition of MIoperandInfo for memr is ptr_rc. From what I can tell memr is used with:

SjLj pseudo-instructions
LXVL/LXVLL vector loads
STXVL/STXVLL vector stores
Based on the ISA, the vector instructions and the LD/LWZ, that the SjLj pseudo-instructions translates to, all require G8RC_NO0X class registers for RA.

[nemanjai]

lib/Target/PowerPC/PPCInstrInfo.td

774 ↗

(On Diff #86303)

Typo. G8RC_NOX0

[hfinkel]

Test case needs some cleanup, otherwise LGTM.

test/CodeGen/PowerPC/sjlj_no0x.ll

31 ↗

(On Diff #86303)

Remove unnecessary attributes.

38 ↗

(On Diff #86303)

Remove unnecessary metadata.

[lei]

lib/Target/PowerPC/PPCInstrInfo.td

774 ↗

(On Diff #86303)

fixed

test/CodeGen/PowerPC/sjlj_no0x.ll

31 ↗

(On Diff #86303)

done

38 ↗

(On Diff #86303)

done

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

 }
 def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getSPE2DisEncoding";
 }
 
 // A single-register address. This is used with the SjLj
-// pseudo-instructions.
+// pseudo-instructions which tranlates to LD/LWZ.  These instructions requires
+// G8RC_NOX0 registers.
 def memr : Operand<iPTR> {
-  let MIOperandInfo = (ops ptr_rc:$ptrreg);
+  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
 }
 def PPCTLSRegOperand : AsmOperandClass {
   let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
   let RenderMethod = "addTLSRegOperands";
 }
 def tlsreg32 : Operand<i32> {
   let EncoderMethod = "getTLSRegEncoding";
   let ParserMatchClass = PPCTLSRegOperand;

llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll

+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: noinline nounwind
+define void @_Z23BuiltinLongJmpFunc1_bufv() #0 {
+entry:
+  call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*))
+  unreachable
+
+; CHECK: @_Z23BuiltinLongJmpFunc1_bufv
+; CHECK: addis [[REG:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld 31, 0([[REG]])
+; CHECK: ld [[REG2:[0-9]+]], 8([[REG]])
+; CHECK-DAG: ld 1, 16([[REG]])
+; CHECK-DAG: ld 30, 32([[REG]])
+; CHECK-DAG: ld 2, 24([[REG]])
+; CHECK-DAG: mtctr [[REG2]]
+; CHECK: bctr
+
+return:                                           ; No predecessors!
+  ret void
+}
+
+; Function Attrs: noreturn nounwind
+declare void @llvm.eh.sjlj.longjmp(i8*) #1