Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -2379,10 +2379,10 @@ return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::NORImm: return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; - case Mips::ADDi: - case Mips::ADDiu: - case Mips::SLTi: - case Mips::SLTiu: + case Mips::ADDi: case Mips::ADDi_MM: + case Mips::ADDiu: case Mips::ADDiu_MM: + case Mips::SLTi: case Mips::SLTi_MM: + case Mips::SLTiu: case Mips::SLTiu_MM: if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { int64_t ImmValue = Inst.getOperand(2).getImm(); @@ -2392,9 +2392,9 @@ : MER_Success; } return MER_NotAMacro; - case Mips::ANDi: - case Mips::ORi: - case Mips::XORi: + case Mips::ANDi: case Mips::ANDi_MM: + case Mips::ORi: case Mips::ORi_MM: + case Mips::XORi: case Mips::XORi_MM: if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) { int64_t ImmValue = Inst.getOperand(2).getImm(); @@ -3821,30 +3821,51 @@ switch (FinalOpcode) { default: llvm_unreachable("unimplemented expansion"); - case (Mips::ADDi): + case Mips::ADDi: FinalOpcode = Mips::ADD; break; - case (Mips::ADDiu): + case Mips::ADDiu: FinalOpcode = Mips::ADDu; break; - case (Mips::ANDi): + case Mips::ANDi: FinalOpcode = Mips::AND; break; - case (Mips::NORImm): + case Mips::NORImm: FinalOpcode = Mips::NOR; break; - case (Mips::ORi): + case Mips::ORi: FinalOpcode = Mips::OR; break; - case (Mips::SLTi): + case Mips::SLTi: FinalOpcode = Mips::SLT; break; - case (Mips::SLTiu): + case Mips::SLTiu: FinalOpcode = Mips::SLTu; break; - case (Mips::XORi): + case Mips::XORi: FinalOpcode = Mips::XOR; break; + case Mips::ADDi_MM: + FinalOpcode = Mips::ADD_MM; + break; + case Mips::ADDiu_MM: + FinalOpcode = Mips::ADDu_MM; + break; + case Mips::ANDi_MM: + FinalOpcode = Mips::AND_MM; + break; + case Mips::ORi_MM: + FinalOpcode = Mips::OR_MM; + break; + case Mips::SLTi_MM: + FinalOpcode = Mips::SLT_MM; + break; + case Mips::SLTiu_MM: + FinalOpcode = Mips::SLTu_MM; + break; + case Mips::XORi_MM: + FinalOpcode = Mips::XOR_MM; + break; } if (FinalDstReg == Mips::NoRegister) Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1136,12 +1136,6 @@ def : MipsInstAlias< "sgtu $rs, $rt", (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; - def : MipsInstAlias<"slt $rs, $rt, $imm", - (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, - simm32_relaxed:$imm), 0>; - def : MipsInstAlias<"sltu $rs, $rt, $imm", - (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, - simm32_relaxed:$imm), 0>; def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sra $rd, $rt, $rs", @@ -1163,18 +1157,21 @@ def : MipsInstAlias<"rotr $rt, $imm", (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; - def : MipsInstAlias<"and $rs, $rt, $imm", - (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; - def : MipsInstAlias<"and $rs, $imm", - (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; - def : MipsInstAlias<"or $rs, $rt, $imm", - (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; - def : MipsInstAlias<"or $rs, $imm", - (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; - def : MipsInstAlias<"xor $rs, $rt, $imm", - (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; - def : MipsInstAlias<"xor $rs, $imm", - (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + + defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>; + + defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>; + + defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>; + + defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>; + + defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>; + + defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>; + + defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>; + def : MipsInstAlias<"not $rt, $rs", (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; def : MipsInstAlias<"not $rt", Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -541,7 +541,7 @@ def SImm32RelaxedAsmOperandClass : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> { let Name = "SImm32_Relaxed"; - let PredicateMethod = "isAnyImm<32>"; + let PredicateMethod = "isAnyImm<33>"; let DiagnosticType = "SImm32_Relaxed"; } def SImm32AsmOperandClass @@ -2320,6 +2320,19 @@ //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// + +multiclass OneOrTwoOperandMacroImmediateAlias { + def : MipsInstAlias; + def : MipsInstAlias; +} + def : MipsInstAlias<"move $dst, $src", (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, GPR_32 { @@ -2332,26 +2345,7 @@ } def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, ISA_MIPS1_NOT_32R6_64R6; -def : MipsInstAlias< - "addu $rs, $rt, $imm", - (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< - "addu $rs, $imm", - (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< - "add $rs, $rt, $imm", - (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>, - ISA_MIPS1_NOT_32R6_64R6; -def : MipsInstAlias< - "add $rs, $imm", - (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>, - ISA_MIPS1_NOT_32R6_64R6; -def : MipsInstAlias< - "and $rs, $rt, $imm", - (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< - "and $rs, $imm", - (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; + def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; let Predicates = [NotInMicroMips] in { def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; @@ -2379,36 +2373,26 @@ "sgtu $$rs, $rt", (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias< - "slt $rs, $rt, $imm", - (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "sltu $rt, $rs, $imm", - (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "and $rs, $rt, $imm", - (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "and $rs, $imm", - (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "xor $rs, $rt, $imm", - (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "xor $rs, $imm", - (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "or $rs, $rt, $imm", - (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< - "or $rs, $imm", - (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; - def : MipsInstAlias< "not $rt, $rs", (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; def : MipsInstAlias< "not $rt", (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>; def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; + + defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6; + + defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>; + + defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>; + + defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>; + + defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>; + + defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>; + + defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>; } def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; @@ -2517,8 +2501,10 @@ "jal\t$rs"> ; def NORImm : MipsAsmPseudoInst< - (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), - "nor\t$rs, $rt, $imm"> ; + (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), + "nor\t$rs, $rt, $imm">; +def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, + simm32_relaxed:$imm)>; let hasDelaySlot = 1, isCTI = 1 in { def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), Index: llvm/trunk/test/MC/Mips/instalias-imm-expanding.s =================================================================== --- llvm/trunk/test/MC/Mips/instalias-imm-expanding.s +++ llvm/trunk/test/MC/Mips/instalias-imm-expanding.s @@ -23,6 +23,10 @@ # CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00] add $4, 0xFFFFFFFF # CHECK: addi $4, $4, -1 # encoding: [0xff,0xff,0x84,0x20] + add $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: add $5, $5, $1 # encoding: [0x20,0x28,0xa1,0x00] add $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -43,6 +47,10 @@ # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] add $4, $5, 0xFFFFFFFF # CHECK: addi $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x20] + add $4, $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] addu $4, -0x80000000 # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] @@ -63,6 +71,10 @@ # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] addu $4, 0xFFFFFFFF # CHECK: addiu $4, $4, -1 # encoding: [0xff,0xff,0x84,0x24] + addu $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: addu $5, $5, $1 # encoding: [0x21,0x28,0xa1,0x00] addu $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -83,6 +95,10 @@ # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] addu $4, $5, 0xFFFFFFFF # CHECK: addiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x24] + addu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] and $4, -0x80000000 # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] @@ -103,6 +119,10 @@ and $4, 0xFFFFFFFF # CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] + and $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: and $5, $5, $1 # encoding: [0x24,0x28,0xa1,0x00] and $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -124,6 +144,10 @@ and $4, $5, 0xFFFFFFFF # CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] + and $4, $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00] nor $4, $5, 0 # CHECK: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] @@ -144,6 +168,34 @@ # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: ori $4, $4, 42405 # encoding: [0xa5,0xa5,0x84,0x34] # CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00] + nor $4, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + + nor $4, 0 +# CHECK: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + nor $4, 1 +# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + nor $4, 0x8000 +# CHECK: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + nor $4, -0x8000 +# CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + nor $4, 0x10000 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + nor $4, 0x1a5a5 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 42405 # encoding: [0xa5,0xa5,0x21,0x34] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] + nor $4, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00] or $4, -0x80000000 # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] @@ -165,6 +217,10 @@ or $4, 0xFFFFFFFF # CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00] + or $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: or $5, $5, $1 # encoding: [0x25,0x28,0xa1,0x00] or $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -186,6 +242,10 @@ or $4, $5, 0xFFFFFFFF # CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] + or $4, $5, ~(0xF0000000|0x0F000000|0x000000F0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00] slt $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -205,6 +265,10 @@ # CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00] slt $4, $5, 0xFFFFFFFF # CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28] + slt $4, $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00] sltu $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -224,6 +288,10 @@ # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] sltu $4, $5, 0xFFFFFFFF # CHECK: sltiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x2c] + sltu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] xor $4, -0x80000000 # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] @@ -244,6 +312,10 @@ xor $4, 0xFFFFFFFF # CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] + xor $4, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34] +# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] xor $4, $5, -0x80000000 # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] @@ -254,7 +326,7 @@ # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] xor $4, $5, -0x8000 # CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24] -# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] +# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] xor $4, $5, 0 # CHECK: xori $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x38] xor $4, $5, 0xFFFF @@ -265,3 +337,7 @@ xor $4, $5, 0xFFFFFFFF # CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00] + xor $4, $5, ~(0xf0000000|0x0f000000|0x000000f0) +# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c] +# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34] +# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]