Index: docs/LangRef.rst
===================================================================
--- docs/LangRef.rst
+++ docs/LangRef.rst
@@ -3627,6 +3627,7 @@
 
 - ``I``: An immediate 13-bit signed integer.
 - ``r``: A 32-bit integer register.
+- ``f``: A 32, 64 or 128-bit float register (``F0-F15``) (for SparcV8)
 
 SystemZ:
 
Index: lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- lib/Target/Sparc/SparcISelLowering.cpp
+++ lib/Target/Sparc/SparcISelLowering.cpp
@@ -3383,7 +3383,9 @@
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default:  break;
-    case 'r': return C_RegisterClass;
+    case 'r':
+    case 'f':
+      return C_RegisterClass;
     case 'I': // SIMM13
       return C_Other;
     }
@@ -3457,6 +3459,18 @@
                                                   MVT VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
+    case 'f':
+      if (VT == MVT::f32)
+        return std::make_pair(0U, &SP::FPRegsRegClass);
+      else if (VT == MVT::f64)
+        return std::make_pair(0U, &SP::DFPRegsRegClass);
+      else if (VT == MVT::f128)
+        return std::make_pair(0U, &SP::QFPRegsRegClass);
+
+      llvm_unreachable("Unknown ValueType for f-register-type!");
+
+      break;
+
     case 'r':
       if (VT == MVT::v2i32)
         return std::make_pair(0U, &SP::IntPairRegClass);
Index: test/CodeGen/SPARC/inlineasm.ll
===================================================================
--- test/CodeGen/SPARC/inlineasm.ll
+++ test/CodeGen/SPARC/inlineasm.ll
@@ -94,3 +94,12 @@
   %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
   ret i64 %0
 }
+
+;; Ensures that inline-asm accepts and uses %f registers
+; CHECK-LABEL: fabsf
+; CHECK: fabss  %f0, %f0
+define float @fabsf(float) local_unnamed_addr #2 {
+entry:
+  %1 = tail call float asm sideeffect "fabss  $1, $0;", "=f,f"(float %0) #7
+  ret float %1
+}