Index: include/llvm/Support/ARMTargetParser.def
===================================================================
--- include/llvm/Support/ARMTargetParser.def
+++ include/llvm/Support/ARMTargetParser.def
@@ -229,6 +229,8 @@
 ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m7", AK_ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-m23", AK_ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-m33", AK_ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
 ARM_CPU_NAME("cortex-a32", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, ARM::AEK_CRC)
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -759,6 +759,16 @@
                                                          FeatureFPARMv8,
                                                          FeatureD16]>;
 
+def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
+                                                         FeatureNoMovt]>;
+
+def : ProcNoItin<"cortex-m33",                          [ARMv8mMainline,
+                                                         FeatureDSP,
+                                                         FeatureT2XtPk,
+                                                         FeatureFPARMv8,
+                                                         FeatureD16,
+                                                         FeatureVFPOnlySP]>;
+
 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
Index: test/CodeGen/ARM/cortex-m23.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/cortex-m23.ll
@@ -0,0 +1,37 @@
+; RUN: llc %s -o - -mtriple=thumbv8m.base -mcpu=cortex-m23 | FileCheck %s
+
+define i32 @test(i32 %Enum_Val_Par, i32* nocapture %Enum_Ref_Par) {
+entry:
+  %call = tail call i32 @Func_3(i32 %Enum_Val_Par)
+  %tobool = icmp ne i32 %call, 0
+  %cond = select i1 %tobool, i32 3, i32 %Enum_Val_Par
+  store i32 %cond, i32* %Enum_Ref_Par, align 4
+; CHECK: cbnz
+; CHECK-NOT: cmp
+; CHECK-NOT: bne
+
+  %tail = tail call i32 @Proc_7(i32 10, i32 %Enum_Val_Par, i32* %Enum_Ref_Par)
+  ret i32 undef
+; CHECK: bl Proc_7
+; CHECK-NOT: b Proc_7
+}
+
+define i32 @test2(i32 %Enum_Val_Par, i32* nocapture %Enum_Ref_Par) {
+entry:
+  %tobool = icmp ne i32 %Enum_Val_Par, 0
+  %cond = select i1 %tobool, i32 3, i32 %Enum_Val_Par
+  store i32 %cond, i32* %Enum_Ref_Par, align 4
+; CHECK: cbnz
+; CHECK-NOT: cmp
+; CHECK-NOT: bne
+
+  %tail = tail call i32 @Proc_7(i32 10, i32 %Enum_Val_Par, i32* %Enum_Ref_Par)
+  ret i32 undef
+; CHECK: b Proc_7
+; CHECK-NOT: bl
+}
+
+declare i32 @Proc_7(i32, i32, i32*)
+
+declare i32 @Func_3(i32)
+
Index: test/CodeGen/ARM/div.ll
===================================================================
--- test/CodeGen/ARM/div.ll
+++ test/CodeGen/ARM/div.ll
@@ -1,15 +1,17 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV -check-prefix=CHECK-SWDIV-64
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift        | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV -check-prefix=CHECK-SWDIV-64 -check-prefix=CHECK-HWDIV-T2
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV -check-prefix=CHECK-SWDIV-64
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f   | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV -check-prefix=CHECK-SWDIV-64
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV -check-prefix=CHECK-SWDIV-64 -check-prefix=CHECK-HWDIV-T2
 ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI -check-prefix=CHECK-EABI-64
+; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-m23 -march=thumb | \
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV -check-prefix=CHECK-EABI-64 -check-prefix=CHECK-HWDIV-T1
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
@@ -41,7 +43,9 @@
 ; CHECK-SWDIV: __modsi3
 
 ; CHECK-HWDIV: sdiv
-; CHECK-HWDIV: mls
+; CHECK-HWDIV-T2-NEXT: mls
+; CHECK-HWDIV-T1-NEXT: muls
+; CHECK-HWDIV-T1-NEXT: subs
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_idivmod
@@ -56,7 +60,9 @@
 ; CHECK-SWDIV: __umodsi3
 
 ; CHECK-HWDIV: udiv
-; CHECK-HWDIV: mls
+; CHECK-HWDIV-T2-NEXT: mls
+; CHECK-HWDIV-T1-NEXT: muls
+; CHECK-HWDIV-T1-NEXT: subs
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_uidivmod
@@ -69,14 +75,12 @@
 define i64 @f5(i64 %a, i64 %b) {
 entry:
 ; CHECK-LABEL: f5
-; CHECK-SWDIV: __moddi3
-
-; CHECK-HWDIV: __moddi3
+; CHECK-SWDIV-64: __moddi3
 
 ; EABI MODE = Remainder in R2-R3, quotient in R0-R1
-; CHECK-EABI: __aeabi_ldivmod
-; CHECK-EABI-NEXT: mov r0, r2
-; CHECK-EABI-NEXT: mov r1, r3
+; CHECK-EABI-64: __aeabi_ldivmod
+; CHECK-EABI-64-NEXT: mov r0, r2
+; CHECK-EABI-64-NEXT: mov r1, r3
         %tmp1 = srem i64 %a, %b         ; <i64> [#uses=1]
         ret i64 %tmp1
 }
@@ -84,14 +88,12 @@
 define i64 @f6(i64 %a, i64 %b) {
 entry:
 ; CHECK-LABEL: f6
-; CHECK-SWDIV: __umoddi3
-
-; CHECK-HWDIV: __umoddi3
+; CHECK-SWDIV-64: __umoddi3
 
 ; EABI MODE = Remainder in R2-R3, quotient in R0-R1
-; CHECK-EABI: __aeabi_uldivmod
-; CHECK-EABI-NEXT: mov r0, r2
-; CHECK-EABI-NEXT: mov r1, r3
+; CHECK-EABI-64: __aeabi_uldivmod
+; CHECK-EABI-64-NEXT: mov r0, r2
+; CHECK-EABI-64-NEXT: mov r1, r3
         %tmp1 = urem i64 %a, %b         ; <i64> [#uses=1]
         ret i64 %tmp1
 }
Index: test/CodeGen/ARM/movt.ll
===================================================================
--- test/CodeGen/ARM/movt.ll
+++ test/CodeGen/ARM/movt.ll
@@ -2,10 +2,14 @@
 ; rdar://7317664
 
 ; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8m.base -mcpu=cortex-m23 %s -o - | FileCheck %s --check-prefix=NOMOVT
 
 define i32 @t(i32 %X) nounwind {
 ; CHECK-LABEL: t:
 ; CHECK: movt r{{[0-9]}}, #65535
+; NOMOVT-LABEL: t:
+; NOMOVT-NOT: movt r{{[0-9]}}, #65535
+; NOMOVT: ldr r{{[0-9]}}, .LCP
 entry:
 	%0 = or i32 %X, -65536
 	ret i32 %0
@@ -14,6 +18,9 @@
 define i32 @t2(i32 %X) nounwind {
 ; CHECK-LABEL: t2:
 ; CHECK: movt r{{[0-9]}}, #65534
+; NOMOVT-LABEL: t2:
+; NOMOVT-NOT: movt r{{[0-9]}}, #65534
+; NOMOVT: ldr r{{[0-9]}}, .LCP
 entry:
 	%0 = or i32 %X, -131072
 	%1 = and i32 %0, -65537
Index: unittests/Support/TargetParserTest.cpp
===================================================================
--- unittests/Support/TargetParserTest.cpp
+++ unittests/Support/TargetParserTest.cpp
@@ -246,6 +246,10 @@
                          ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                          ARM::AEK_HWDIV | ARM::AEK_DSP,
                          "8-A"));
+  EXPECT_TRUE(testARMCPU("cortex-m23", "armv8-m.base", "none",
+                         ARM::AEK_HWDIV, "8-M.Baseline"));
+  EXPECT_TRUE(testARMCPU("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
+                         ARM::AEK_HWDIV | ARM::AEK_DSP, "8-M.Mainline"));
   EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
                          ARM::AEK_NONE, "iwmmxt"));
   EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",