Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2050,6 +2050,16 @@ if (Cond == ISD::SETO || Cond == ISD::SETUO) return DAG.getSetCC(dl, VT, N0, N0, Cond); + // setcc (fneg x), C -> setcc swap(pred) x, -C + if (N0.getOpcode() == ISD::FNEG) { + ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond); + if (DCI.isBeforeLegalizeOps() || + isCondCodeLegal(SwapCond, N0.getSimpleValueType())) { + SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1); + return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond); + } + } + // If the condition is not legal, see if we can find an equivalent one // which is legal. if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { Index: test/CodeGen/AMDGPU/setcc-fneg-constant.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/setcc-fneg-constant.ll @@ -0,0 +1,257 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s + +; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine. + +; GCN-LABEL: {{^}}multi_use_fneg_src: +; GCN: buffer_load_dword [[A:v[0-9]+]] +; GCN: buffer_load_dword [[B:v[0-9]+]] +; GCN: buffer_load_dword [[C:v[0-9]+]] + +; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]] +; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL]] +; GCN: buffer_store_dword [[MUL]] +define void @multi_use_fneg_src() #0 { + %a = load volatile float, float addrspace(1)* undef + %b = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + + %mul = fmul float %a, %b + %neg.mul = fsub float -0.0, %mul + %cmp = fcmp oeq float %neg.mul, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + store volatile float %mul, float addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}multi_foldable_use_fneg_src: +; GCN: buffer_load_dword [[A:v[0-9]+]] +; GCN: buffer_load_dword [[B:v[0-9]+]] +; GCN: buffer_load_dword [[C:v[0-9]+]] + +; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]] +; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[A]] +; GCN: v_mul_f32_e64 [[USE1:v[0-9]+]], [[MUL]], -[[MUL]] +define void @multi_foldable_use_fneg_src() #0 { + %a = load volatile float, float addrspace(1)* undef + %b = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + + %mul = fmul float %a, %b + %neg.mul = fsub float -0.0, %mul + %use1 = fmul float %mul, %neg.mul + %cmp = fcmp oeq float %neg.mul, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + + store volatile i32 %select, i32 addrspace(1)* undef + store volatile float %use1, float addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}multi_use_fneg: +; GCN: buffer_load_dword [[A:v[0-9]+]] +; GCN: buffer_load_dword [[B:v[0-9]+]] +; GCN: buffer_load_dword [[C:v[0-9]+]] + +; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], [[A]], -[[B]] +; GCN: v_cmp_eq_f32_e32 vcc, 4.0, [[MUL]] +; GCN: buffer_store_dword [[MUL]] +define void @multi_use_fneg() #0 { + %a = load volatile float, float addrspace(1)* undef + %b = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + + %mul = fmul float %a, %b + %neg.mul = fsub float -0.0, %mul + %cmp = fcmp oeq float %neg.mul, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + store volatile float %neg.mul, float addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}multi_foldable_use_fneg: +; GCN: buffer_load_dword [[A:v[0-9]+]] +; GCN: buffer_load_dword [[B:v[0-9]+]] + +; GCN: v_mul_f32_e32 [[MUL0:v[0-9]+]], [[B]], [[A]] +; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL0]] +; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MUL0]], [[MUL0]] +; GCN: buffer_store_dword [[MUL1]] +define void @multi_foldable_use_fneg() #0 { + %a = load volatile float, float addrspace(1)* undef + %b = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %z = load volatile i32, i32 addrspace(1)* undef + + %mul = fmul float %a, %b + %neg.mul = fsub float -0.0, %mul + %cmp = fcmp oeq float %neg.mul, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + %use1 = fmul float %neg.mul, %mul + store volatile i32 %select, i32 addrspace(1)* undef + store volatile float %use1, float addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_oeq_posk_f32: +; GCN: v_cmp_eq_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_oeq_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp oeq float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_ogt_posk_f32: +; GCN: v_cmp_gt_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_ogt_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp ogt float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_oge_posk_f32: +; GCN: v_cmp_ge_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_oge_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp oge float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_olt_posk_f32: +; GCN: v_cmp_lt_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_olt_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp olt float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_ole_posk_f32: +; GCN: v_cmp_le_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_ole_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp ole float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_one_posk_f32: +; GCN: v_cmp_lg_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_one_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp one float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_ueq_posk_f32: +; GCN: v_cmp_nlg_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_ueq_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp ueq float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_ugt_posk_f32: +; GCN: v_cmp_nle_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_ugt_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp ugt float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_uge_posk_f32: +; GCN: v_cmp_nlt_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_uge_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp uge float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_ult_posk_f32: +; GCN: v_cmp_nge_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_ult_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp ult float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_ule_posk_f32: +; GCN: v_cmp_ngt_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_ule_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp ule float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}test_setcc_fneg_une_posk_f32: +; GCN: v_cmp_neq_f32_e32 vcc, -4.0, v{{[0-9]+}} +define void @test_setcc_fneg_une_posk_f32() #0 { + %a = load volatile float, float addrspace(1)* undef + %x = load volatile i32, i32 addrspace(1)* undef + %y = load volatile i32, i32 addrspace(1)* undef + %neg.a = fsub float -0.0, %a + %cmp = fcmp une float %neg.a, 4.0 + %select = select i1 %cmp, i32 %x, i32 %y + store volatile i32 %select, i32 addrspace(1)* undef + ret void +} + +attributes #0 = { nounwind } Index: test/CodeGen/SystemZ/fp-cmp-05.ll =================================================================== --- test/CodeGen/SystemZ/fp-cmp-05.ll +++ test/CodeGen/SystemZ/fp-cmp-05.ll @@ -9,7 +9,7 @@ ; Test f32 define float @f1(float %a, float %b, float %f) { ; CHECK-LABEL: f1: -; CHECK: lcebr +; CHECK: ltebr ; CHECK-NEXT: ber %r14 %neg = fsub float -0.0, %f %cond = fcmp oeq float %neg, 0.0 @@ -20,7 +20,7 @@ ; Test f64 define double @f2(double %a, double %b, double %f) { ; CHECK-LABEL: f2: -; CHECK: lcdbr +; CHECK: ltdbr ; CHECK-NEXT: ber %r14 %neg = fsub double -0.0, %f %cond = fcmp oeq double %neg, 0.0 @@ -33,7 +33,7 @@ declare float @llvm.fabs.f32(float %f) define float @f3(float %a, float %b, float %f) { ; CHECK-LABEL: f3: -; CHECK: lnebr +; CHECK: lpebr ; CHECK-NEXT: ber %r14 %abs = call float @llvm.fabs.f32(float %f) %neg = fsub float -0.0, %abs @@ -46,7 +46,7 @@ declare double @llvm.fabs.f64(double %f) define double @f4(double %a, double %b, double %f) { ; CHECK-LABEL: f4: -; CHECK: lndbr +; CHECK: lpdbr ; CHECK-NEXT: ber %r14 %abs = call double @llvm.fabs.f64(double %f) %neg = fsub double -0.0, %abs Index: test/CodeGen/XCore/fneg.ll =================================================================== --- test/CodeGen/XCore/fneg.ll +++ test/CodeGen/XCore/fneg.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -march=xcore | FileCheck %s -define i1 @test(double %F) nounwind { +define i1 @test(double %F, double %G) nounwind { entry: ; CHECK-LABEL: test: ; CHECK: xor %0 = fsub double -0.000000e+00, %F - %1 = fcmp olt double 0.000000e+00, %0 + %1 = fcmp olt double %G, %0 ret i1 %1 }