Index: lib/Target/NDS32/CMakeLists.txt =================================================================== --- lib/Target/NDS32/CMakeLists.txt +++ lib/Target/NDS32/CMakeLists.txt @@ -4,6 +4,7 @@ tablegen(LLVM NDS32GenRegisterInfo.inc -gen-register-info) tablegen(LLVM NDS32GenInstrInfo.inc -gen-instr-info) tablegen(LLVM NDS32GenDAGISel.inc -gen-dag-isel) +tablegen(LLVM NDS32GenCallingConv.inc -gen-callingconv) add_public_tablegen_target(NDS32CommonTableGen) @@ -16,6 +17,7 @@ NDS32InstrInfo.cpp NDS32ISelDAGToDAG.cpp NDS32ISelLowering.cpp + NDS32MachineFunctionInfo.cpp ) add_subdirectory(TargetInfo) Index: lib/Target/NDS32/NDS32.td =================================================================== --- lib/Target/NDS32/NDS32.td +++ lib/Target/NDS32/NDS32.td @@ -38,6 +38,12 @@ include "NDS32RegisterInfo.td" //===----------------------------------------------------------------------===// +// Calling Convention Description +//===----------------------------------------------------------------------===// + +include "NDS32CallingConv.td" + +//===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// Index: lib/Target/NDS32/NDS32CallingConv.td =================================================================== --- /dev/null +++ lib/Target/NDS32/NDS32CallingConv.td @@ -0,0 +1,74 @@ +//==- NDS32CallingConv.td - Calling Conventions for NDS32 -*- tablegen -*---==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This describes the calling conventions for NDS32 architecture. +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// NDS32 Return Value Calling Convention +//===----------------------------------------------------------------------===// +def RetCC_NDS32_SoftFloat : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType>, + CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, + CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>, + + CCIfType<[f32], CCBitConvertToType> +]>; + +def RetCC_NDS32 : CallingConv<[ + CCDelegateTo +]>; + +//===----------------------------------------------------------------------===// +// NDS32 Argument Calling Conventions +//===----------------------------------------------------------------------===// + +/// CCIfAlign - Match of the original alignment of the arg +class CCIfAlign: + CCIf; + +class CCIfNotAlign: + CCIf; + +def CC_NDS32_SoftFloat : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType>, + + // Pass by value if the byval attribute is given + CCIfByVal>, + + // The first to sixth argument are passed with register R0 ~ R5. + // Not align to 8 byte mean it's i32 or f32 + CCIfType<[i32], CCIfNotAlign<"8", CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>>, + // Align to 8 byte mean it's i64 or f64, it's passed in even pairs of GPRs + // need to pad R1/R3 if assign to R2/R4. + CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2, R4], + [R0, R1, R3]>>>, + + // If a part of argument assign to stack, shadow the argument registers. + // To avoid a double argument assign to stack and register in the same time. + CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, + R3, R4, R5]>>>, + + CCIfType<[f32], CCBitConvertToType>, + CCIfType<[i64, f64], CCAssignToRegWithShadow<[R0, R2, R4], [R1, R3, R5]>>, + + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + CCIfType<[i64, f64], CCAssignToStack<8, 8>> +]>; + +def CC_NDS32 : CallingConv<[ + CCDelegateTo +]>; + + +//===----------------------------------------------------------------------===// +// Callee-saved register lists. +//===----------------------------------------------------------------------===// + +// Callee save registers for V3 Architecture +def CSR_V3 : CalleeSavedRegs<(add LP, FP, (sequence "R%u", 14, 6))>; Index: lib/Target/NDS32/NDS32ISelLowering.h =================================================================== --- lib/Target/NDS32/NDS32ISelLowering.h +++ lib/Target/NDS32/NDS32ISelLowering.h @@ -112,6 +112,11 @@ SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl &InVals) const override; + + SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, + const SDLoc &dl, SelectionDAG &DAG) const override; }; } // namespace llvm Index: lib/Target/NDS32/NDS32ISelLowering.cpp =================================================================== --- lib/Target/NDS32/NDS32ISelLowering.cpp +++ lib/Target/NDS32/NDS32ISelLowering.cpp @@ -15,6 +15,7 @@ #include "NDS32.h" #include "NDS32Subtarget.h" #include "NDS32TargetMachine.h" +#include "NDS32MachineFunctionInfo.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -255,15 +256,149 @@ // Calling Convention Implementation //===----------------------------------------------------------------------===// +#include "NDS32GenCallingConv.inc" + +// addLiveIn - This helper function adds the specified physical register to the +// MachineFunction as a live in value. It also creates a corresponding +// virtual register for it. +static unsigned +addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) +{ + unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); + MF.getRegInfo().addLiveIn(PReg, VReg); + return VReg; +} + +static const MCPhysReg NDS32ArgRegs[6] = { + NDS32::R0, NDS32::R1, NDS32::R2, + NDS32::R3, NDS32::R4, NDS32::R5 +}; + // LowerFormalArguments - Specify how callee get arguments SDValue NDS32TargetLowering::LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + NDS32MachineFunctionInfo *FI = MF.getInfo(); + + FI->setVarArgsFrameIndex(0); + + // Used with vargs to accumulate store chains. + std::vector OutChains; + + // Assign locations to all of the incoming arguments. + SmallVector ArgLocs; + + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); + + const Function *Func = DAG.getMachineFunction().getFunction(); + Function::const_arg_iterator FuncArg = Func->arg_begin(); + + CCInfo.AnalyzeFormalArguments(Ins, CC_NDS32_SoftFloat); + + unsigned CurArgIdx = 0; + + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + if (Ins[i].isOrigArg()) { + std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[i].getOrigArgIndex(); + } + ISD::ArgFlagsTy Flags = Ins[i].Flags; + bool IsRegLoc = VA.isRegLoc(); + // Arguments stored on registers + if (IsRegLoc) { + MVT RegVT = VA.getLocVT(); + unsigned ArgReg = VA.getLocReg(); + const TargetRegisterClass *RC = getRegClassFor(RegVT); + + // Transform the arguments stored on + // physical registers into virtual ones + unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); + + InVals.push_back(ArgValue); + } else { // VA.isRegLoc() + MVT LocVT = VA.getLocVT(); + + // sanity check + assert(VA.isMemLoc()); + + // The stack pointer offset is relative to the caller stack frame. + int FrameIdx = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, + VA.getLocMemOffset(), true); + // Create load nodes to retrieve arguments from the stack + SDValue FIN = DAG.getFrameIndex(FrameIdx, + getPointerTy(DAG.getDataLayout())); + SDValue ArgValue = DAG.getLoad( + LocVT, DL, Chain, FIN, + MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), + FrameIdx)); + OutChains.push_back(ArgValue.getValue(1)); + + InVals.push_back(ArgValue); + } + } + + // All stores are grouped in one node to allow the matching between + // the size of Ins and InVals. This only happens when on varg functions + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } return Chain; } +// LowerReturn - Specify how callee return value +SDValue +NDS32TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, + const SDLoc &dl, SelectionDAG &DAG) const { + + // CCValAssign - represent the assignment of the return value to a location + SmallVector RVLocs; + + // CCState - Info about the registers and stack slot. + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); + + // Analize return values. + CCInfo.AnalyzeReturn(Outs, RetCC_NDS32); + + SDValue Flag; + SmallVector RetOps(1, Chain); + + // Copy the result values into the output registers. + for (unsigned i = 0; i != RVLocs.size(); ++i) { + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + OutVals[i], Flag); + + // Guarantee that all emitted copies are stuck together, + // avoiding something bad. + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + + unsigned Opc = NDS32ISD::RET; + + RetOps[0] = Chain; // Update chain. + + // Add the flag if we have it. + if (Flag.getNode()) + RetOps.push_back(Flag); + + return DAG.getNode(Opc, dl, MVT::Other, RetOps); +} + // LowerCall - Specify how caller passing arguments SDValue NDS32TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Index: lib/Target/NDS32/NDS32InstrFormats.td =================================================================== --- lib/Target/NDS32/NDS32InstrFormats.td +++ lib/Target/NDS32/NDS32InstrFormats.td @@ -34,6 +34,9 @@ let Inst{30-25} = opcode; } +class JREGForm pattern> + : 32BitInst<0b100101, outs, ins, asmstr, pattern>; + // Pseudo instructions class Pseudo pattern> : 32BitInst<0b110010, outs, ins, asmstr, pattern> { Index: lib/Target/NDS32/NDS32InstrInfo.td =================================================================== --- lib/Target/NDS32/NDS32InstrInfo.td +++ lib/Target/NDS32/NDS32InstrInfo.td @@ -22,6 +22,8 @@ //===----------------------------------------------------------------------===// // NDS32 Specific Node Definitions. //===----------------------------------------------------------------------===// +def NDS32ret : SDNode<"NDS32ISD::RET", SDTNone, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def NDS32callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NDS32CallSeqStart, [SDNPHasChain, SDNPOutGlue]>; @@ -43,3 +45,17 @@ "#ADJCALLSTACKUP", [(NDS32callseq_end timm:$amt1, timm:$amt2)]>; } + +class JREG_ret pat, bits<2> dt_it> : + JREGForm<(outs), (ins), opstr, pat> { + let Inst{24-15} = 0; + let Inst{14-10} = 30; // LP register number + let Inst{9-8} = dt_it; // DT/IT + let Inst{7-6} = 0; + let Inst{5} = 1; + let Inst{4-0} = 0; +} + +let isReturn = 1, isTerminator = 1, isBarrier = 1 in { + def RET : JREG_ret<"ret", [(NDS32ret)], 0b00>; +} Index: lib/Target/NDS32/NDS32MachineFunctionInfo.h =================================================================== --- /dev/null +++ lib/Target/NDS32/NDS32MachineFunctionInfo.h @@ -0,0 +1,54 @@ +//=== NDS32MachineFunctionInfo.h - NDS32 machine function info -*- C++ -*---==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares NDS32-specific per-machine-function information. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_NDS32_NDS32MACHINEFUNCTIONINFO_H +#define LLVM_LIB_TARGET_NDS32_NDS32MACHINEFUNCTIONINFO_H + +#include "llvm/CodeGen/MachineFunction.h" + +namespace llvm { + +/// NDS32MachineFunctionInfo - This class is derived from MachineFunction and +/// contains private NDS32 target-specific information for each MachineFunction. +class NDS32MachineFunctionInfo : public MachineFunctionInfo { + virtual void anchor(); + + /// CalleeSavedFrameSize - Size of the callee-saved register portion of the + /// stack frame in bytes. + unsigned CalleeSavedFrameSize; + + /// ReturnAddrIndex - FrameIndex for return slot. + int ReturnAddrIndex; + + /// VarArgsFrameIndex - FrameIndex for start of varargs area. + int VarArgsFrameIndex; + +public: + NDS32MachineFunctionInfo() : CalleeSavedFrameSize(0) {} + + explicit NDS32MachineFunctionInfo(MachineFunction &MF) + : CalleeSavedFrameSize(0), ReturnAddrIndex(0) {} + + unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; } + void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; } + + int getRAIndex() const { return ReturnAddrIndex; } + void setRAIndex(int Index) { ReturnAddrIndex = Index; } + + int getVarArgsFrameIndex() const { return VarArgsFrameIndex;} + void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/NDS32/NDS32MachineFunctionInfo.cpp =================================================================== --- /dev/null +++ lib/Target/NDS32/NDS32MachineFunctionInfo.cpp @@ -0,0 +1,14 @@ +//===-- NDS32MachineFunctionInfo.cpp - NDS32 machine function info --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "NDS32MachineFunctionInfo.h" + +using namespace llvm; + +void NDS32MachineFunctionInfo::anchor() { } Index: lib/Target/NDS32/NDS32RegisterInfo.cpp =================================================================== --- lib/Target/NDS32/NDS32RegisterInfo.cpp +++ lib/Target/NDS32/NDS32RegisterInfo.cpp @@ -36,13 +36,13 @@ const MCPhysReg* NDS32RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - return nullptr; + return CSR_V3_SaveList; } const uint32_t * NDS32RegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const { - return nullptr; + return CSR_V3_RegMask; } BitVector NDS32RegisterInfo::getReservedRegs(const MachineFunction &MF) const {