Index: lib/Target/NDS32/NDS32Instr16Bit.td
===================================================================
--- /dev/null
+++ lib/Target/NDS32/NDS32Instr16Bit.td
@@ -0,0 +1,276 @@
+//===-- NDS32InstrInfo.td - NDS32 16 bit Instruction defs --*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the NDS32 16 bit instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Control Flow Instructions
+//
+
+def BEQZ38 : BEQZ38Form<(outs), (ins lGPR:$Rt, brtargetImm8s:$offset),
+                        "beqz38\t$Rt, $offset",
+                        [(brcond (i32 (seteq lGPR:$Rt, 0)), bb:$offset)]>,
+                        Requires<[Has16Bit]> {
+  let isBranch = 1;
+  let isTerminator = 1;
+}
+
+def BNEZ38 : BNEZ38Form<(outs), (ins lGPR:$Rt, brtargetImm8s:$offset),
+                        "bnez38\t$Rt, $offset",
+                        [(brcond (i32 (setne lGPR:$Rt, 0)), bb:$offset)]>,
+                        Requires<[Has16Bit]> {
+  let isBranch = 1;
+  let isTerminator = 1;
+}
+
+let isBranch = 1, isTerminator = 1, isBarrier=1 in {
+
+  // Unconditional jump
+  def J8  : J8Form<(outs), (ins brtargetImm8s:$target),
+                   "j8\t$target",
+                   [(br bb:$target)]>,
+                   Requires<[Has16Bit]>;
+  // Unconditional jump to to the target in register
+  def JR5  : JR5Form<(outs), (ins GPR:$Rb),
+                     "jr5\t$Rb",
+                     [(brind GPR:$Rb)]>,
+                     Requires<[Has16Bit]> {
+    let isIndirectBranch = 1;
+  }
+} // isBranch, isTerminator
+
+let isCall = 1,
+  Defs = [LP] in {
+  def JRAL5  : JRAL5Form<(outs), (ins GPR:$Rb),
+                         "jral5\t$Rb",
+                         [(NDS32call GPR:$Rb)]>,
+                         Requires<[Has16Bit]>;
+}
+
+let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
+  def RET5  : RET5Form<(outs), (ins), "ret5", [(NDS32ret)]>,
+                       Requires<[Has16Bit]>;
+}
+
+
+//===----------------------------------------------------------------------===//
+// Arithmetic Instructions
+//
+
+let isAdd = 1 in
+def ADD333 : ADD333Form<(outs lGPR:$Rt), (ins lGPR:$Ra, lGPR:$Rb),
+                        "add333\t$Rt, $Ra, $Rb",
+                        [(set lGPR:$Rt, (add lGPR:$Ra, lGPR:$Rb))]>,
+                        Requires<[Has16Bit]>;
+
+let isAdd = 1 in
+def ADD45 : ADD45Form<(outs mGPR:$Rt_wb), (ins mGPR:$Rt, GPR:$Rb),
+                      "add45\t$Rt, $Rb",
+                      [(set mGPR:$Rt_wb, (add mGPR:$Rt, GPR:$Rb))]>,
+                      Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+let isAdd = 1 in
+def ADDI333 : ADDI333Form<(outs lGPR:$Rt), (ins lGPR:$Ra, imm3u:$imm),
+                          "addi333\t$Rt, $Ra, $imm",
+                          [(set lGPR:$Rt, (add lGPR:$Ra, imm3u:$imm))]>,
+                          Requires<[Has16Bit]>;
+
+let isAdd = 1 in
+def ADDI45 : ADDI45Form<(outs mGPR:$Rt_wb), (ins mGPR:$Rt, imm5u:$imm),
+                        "addi45\t$Rt, $imm",
+                        [(set mGPR:$Rt_wb, (add mGPR:$Rt, imm5u:$imm))]>,
+                        Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+def SUB333 : SUB333Form<(outs lGPR:$Rt), (ins lGPR:$Ra, lGPR:$Rb),
+                        "sub333\t$Rt, $Ra, $Rb",
+                        [(set lGPR:$Rt, (sub lGPR:$Ra, lGPR:$Rb))]>,
+                        Requires<[Has16Bit]>;
+
+def SUB45 : SUB45Form<(outs mGPR:$Rt_wb), (ins mGPR:$Rt, GPR:$Rb),
+                      "sub45\t$Rt, $Rb",
+                      [(set mGPR:$Rt_wb, (sub mGPR:$Rt, GPR:$Rb))]>,
+                      Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+def SUBI333 : SUBI333Form<(outs lGPR:$Rt), (ins lGPR:$Ra, imm3u:$imm),
+                          "subi333\t$Rt, $Ra, $imm",
+                          [(set lGPR:$Rt, (sub lGPR:$Ra, imm3u:$imm))]>,
+                          Requires<[Has16Bit]>;
+
+def SUBI45 : SUBI45Form<(outs mGPR:$Rt_wb), (ins mGPR:$Rt, imm5u:$imm),
+                        "subi45\t$Rt, $imm",
+                        [(set mGPR:$Rt_wb, (sub mGPR:$Rt, imm5u:$imm))]>,
+                        Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+class  BFMI333_sextend <string opstr, SDPatternOperator Op,
+                        ValueType vt, bits<3> subop_encode> :
+  BFMI333Form<(outs lGPR:$Rt), (ins lGPR:$Ra),
+              !strconcat(opstr, "\t$Rt, $Ra"),
+              [(set lGPR:$Rt, (Op lGPR:$Ra, vt))],
+              subop_encode>,
+              Requires<[Has16Bit]>;
+
+def SEB33     : BFMI333_sextend< "seb33",    sext_inreg,  i8, 0b010>;
+def SEH33     : BFMI333_sextend< "seh33",    sext_inreg, i16, 0b011>;
+
+
+def SLLI333: SLLI333Form<(outs lGPR:$Rt), (ins lGPR:$Ra, imm3u:$imm),
+                         "slli333\t$Rt, $Ra, $imm",
+                         [(set lGPR:$Rt, (shl lGPR:$Ra, imm3u:$imm))]>,
+                         Requires<[Has16Bit]>;
+
+def SRAI45 : SRAI45Form<(outs mGPR:$Rt_wb), (ins mGPR:$Rt, imm5u:$imm),
+                        "srai45\t$Rt, $imm",
+                        [(set mGPR:$Rt_wb, (sra mGPR:$Rt, imm5u:$imm))]>,
+                        Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+def SRLI45 : SRLI45Form<(outs mGPR:$Rt_wb), (ins mGPR:$Rt, imm5u:$imm),
+                        "srli45\t$Rt, $imm",
+                        [(set mGPR:$Rt_wb, (srl mGPR:$Rt, imm5u:$imm))]>,
+                        Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+class  BFMI333_andi <string opstr, bits<3> subop_encode> :
+  BFMI333Form<(outs lGPR:$Rt), (ins lGPR:$Ra),
+              !strconcat(opstr, "\t$Rt, $Ra"), [],
+              subop_encode>,
+              Requires<[Has16Bit]>;
+
+def X11B33     : BFMI333_andi< "x11b33", 0b101>;
+def XLSB33     : BFMI333_andi< "xlsb33", 0b100>;
+def ZEB33      : BFMI333_andi< "zeb33",  0b000>;
+def ZEH33      : BFMI333_andi< "zeh33",  0b001>;
+
+
+class  ALU33 <string opstr, SDPatternOperator Op, bits<3> subop_encode> :
+  MISC33Form<(outs lGPR:$Rt_wb), (ins lGPR:$Rt, lGPR:$Ra),
+             !strconcat(opstr, "\t$Rt, $Ra"),
+             [(set lGPR:$Rt_wb, (Op lGPR:$Rt, lGPR:$Ra))],
+             subop_encode>,
+             Requires<[Has16Bit]> {
+  let Constraints = "$Rt = $Rt_wb";
+}
+
+def AND33     : ALU33< "and33", and, 0b110>;
+def MUL33     : ALU33< "mul33", mul, 0b100>;
+def OR33      : ALU33< "or33" ,  or, 0b111>;
+def XOR33     : ALU33< "xor33", xor, 0b101>;
+
+def NOT33 : MISC33Form<(outs lGPR:$Rt), (ins lGPR:$Ra),
+                       "not33\t$Rt, $Ra",
+                       [(set lGPR:$Rt, (not lGPR:$Ra))], 0b011>,
+                       Requires<[Has16Bit]>;
+
+
+//===----------------------------------------------------------------------===//
+// Move Instructions
+//
+
+def MOV55: MOV55Form<(outs GPR:$Rt), (ins GPR:$Ra),
+                     "mov55\t$Rt, $Ra", []>,
+                     Requires<[Has16Bit]>;
+
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
+def MOVI55 : MOVI55Form<(outs GPR:$Rt), (ins imm5s:$imm),
+                        "movi55\t$Rt, $imm",
+                        [(set GPR:$Rt, (imm5s:$imm))]>,
+                        Requires<[Has16Bit]>;
+
+
+//===----------------------------------------------------------------------===//
+// Load/Store Instructions
+//
+
+let AddedComplexity = 4 in {
+def LBI333: LBI333Form<(outs lGPR:$Rt), (ins addr_imm3u_byte:$addr),
+                       "lbi333\t$Rt, $addr",
+                       [(set lGPR:$Rt, (zextloadi8 addr_imm3u_byte:$addr))]>,
+                       Requires<[Has16Bit]>;
+
+def LHI333: LHI333Form<(outs lGPR:$Rt), (ins addr_imm3u_half:$addr),
+                       "lhi333\t$Rt, $addr",
+                       [(set lGPR:$Rt, (zextloadi16 addr_imm3u_half:$addr))]>,
+                       Requires<[Has16Bit]>;
+
+def LWI333: LWI333Form<(outs lGPR:$Rt), (ins addr_imm3u_word:$addr),
+                       "lwi333\t$Rt, $addr",
+                       [(set lGPR:$Rt, (load addr_imm3u_word:$addr))]>,
+                       Requires<[Has16Bit]>;
+
+def LWI450: LWI450Form<(outs mGPR:$Rt), (ins addr_reg:$addr),
+                       "lwi450\t$Rt, $addr",
+                       [(set mGPR:$Rt, (load addr_reg:$addr))]>,
+                       Requires<[Has16Bit]>;
+
+
+def SBI333: SBI333Form<(outs), (ins lGPR:$Rt, addr_imm3u_byte:$addr),
+                       "sbi333\t$Rt, $addr",
+                       [(truncstorei8 lGPR:$Rt, addr_imm3u_byte:$addr)]>,
+                       Requires<[Has16Bit]>;
+
+def SHI333: SHI333Form<(outs), (ins lGPR:$Rt, addr_imm3u_half:$addr),
+                       "shi333\t$Rt, $addr",
+                       [(truncstorei16 lGPR:$Rt, addr_imm3u_half:$addr)]>,
+                       Requires<[Has16Bit]>;
+
+def SWI333: SWI333Form<(outs), (ins lGPR:$Rt, addr_imm3u_word:$addr),
+                       "swi333\t$Rt, $addr",
+                       [(store lGPR:$Rt, addr_imm3u_word:$addr)]>,
+                       Requires<[Has16Bit]>;
+
+def SWI450: SWI450Form<(outs), (ins  mGPR:$Rt, addr_reg:$addr),
+                       "swi450\t$Rt, $addr",
+                       [(store mGPR:$Rt, addr_reg:$addr)]>,
+                       Requires<[Has16Bit]>;
+
+def LWI37: XWI37Form<(outs lGPR:$Rt), (ins addr_fp_base_offset_imm7u_word:$addr),
+                     "lwi37\t$Rt, $addr", [], 0>,
+                     Requires<[Has16Bit]>;
+
+def SWI37: XWI37Form<(outs lGPR:$Rt), (ins addr_fp_base_offset_imm7u_word:$addr),
+                     "swi37\t$Rt, $addr", [], 1>,
+                     Requires<[Has16Bit]>;
+
+def LWI37SP: XWI37SPForm<(outs lGPR:$Rt), (ins addr_sp_base_offset_imm7u_word:$addr),
+                         "lwi37.sp\t$Rt, $addr", [], 0>,
+                         Requires<[Has16Bit]>;
+
+def SWI37SP: XWI37SPForm<(outs lGPR:$Rt), (ins addr_sp_base_offset_imm7u_word:$addr),
+                         "swi37.sp\t$Rt, $addr", [], 1>,
+                         Requires<[Has16Bit]>;
+}
+
+//===----------------------------------------------------------------------===//
+// Pattern Transformation
+//===----------------------------------------------------------------------===//
+
+// brcond patterns
+def : NDS16Pat<(brcond lGPR:$cond, bb:$dst),
+               (BNEZ38 lGPR:$cond, bb:$dst)>;
+
+def : NDS16Pat<(and lGPR:$Ra, 0x7ff),
+               (X11B33 lGPR:$Ra)>;
+def : NDS16Pat<(and lGPR:$Ra, 0x1),
+               (XLSB33 lGPR:$Ra)>;
+def : NDS16Pat<(and lGPR:$Ra, 0xff),
+               (ZEB33 lGPR:$Ra)>;
+def : NDS16Pat<(and lGPR:$Ra, 0xffff),
+               (ZEH33 lGPR:$Ra)>;
Index: lib/Target/NDS32/NDS32Instr16Formats.td
===================================================================
--- /dev/null
+++ lib/Target/NDS32/NDS32Instr16Formats.td
@@ -0,0 +1,335 @@
+//===-- NDS32Instr16Formats.td - NDS32 Instruction Formats -*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Describe NDS32 16 bit instructions format here
+//
+
+class 16BitInst4BitOpcode<bits<4> opcode,
+                dag outs, dag ins, string asmstr, list<dag> pattern>
+  : NDS32Inst<outs, ins, asmstr> {
+  field bits<16> Inst;
+  let Size = 2;
+  let Pattern = pattern;
+
+  let Inst{15} = 1;
+  let Inst{14-11} = opcode;
+}
+
+class 16BitInst5BitOpcode<bits<5> opcode,
+                dag outs, dag ins, string asmstr, list<dag> pattern>
+  : NDS32Inst<outs, ins, asmstr> {
+  field bits<16> Inst;
+  let Size = 2;
+  let Pattern = pattern;
+
+  let Inst{15} = 1;
+  let Inst{14-10} = opcode;
+}
+
+class 16BitInst6BitOpcode<bits<6> opcode,
+                dag outs, dag ins, string asmstr, list<dag> pattern>
+  : NDS32Inst<outs, ins, asmstr> {
+  field bits<16> Inst;
+  let Size = 2;
+  let Pattern = pattern;
+
+  let Inst{15} = 1;
+  let Inst{14-9} = opcode;
+}
+
+class 16BitInst7BitOpcode<bits<7> opcode,
+                dag outs, dag ins, string asmstr, list<dag> pattern>
+  : NDS32Inst<outs, ins, asmstr> {
+  field bits<16> Inst;
+  let Size = 2;
+  let Pattern = pattern;
+
+  let Inst{15} = 1;
+  let Inst{14-8} = opcode;
+}
+
+class 16BitInst10BitOpcode<bits<10> opcode,
+                dag outs, dag ins, string asmstr, list<dag> pattern>
+  : NDS32Inst<outs, ins, asmstr> {
+  field bits<16> Inst;
+  let Size = 2;
+  let Pattern = pattern;
+
+  let Inst{15} = 1;
+  let Inst{14-5} = opcode;
+}
+
+class ADD333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001100, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  bits<3> Rb;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = Rb;
+}
+
+class ADD45Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b000100, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> Rb;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = Rb;
+}
+
+class ADDI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001110, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  bits<3> imm;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = imm;
+}
+
+class ADDI45Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b000110, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> imm;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = imm;
+}
+
+class BEQZ38Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst4BitOpcode<0b1000, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<8> offset;
+  let Inst{10-8} = Rt;
+  let Inst{7-0} = offset;
+}
+
+class BNEZ38Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst4BitOpcode<0b1001, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<8> offset;
+  let Inst{10-8} = Rt;
+  let Inst{7-0} = offset;
+}
+
+class J8Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst7BitOpcode<0b1010101, outs, ins, asmstr, pattern> {
+  bits<8> target;
+  let Inst{7-0} = target;
+}
+
+class JR5Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst10BitOpcode<0b1011101000, outs, ins, asmstr, pattern> {
+  bits<5> Rb;
+  let Inst{4-0} = Rb;
+}
+
+class JRAL5Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst10BitOpcode<0b1011101001, outs, ins, asmstr, pattern> {
+  bits<5> Rb;
+  let Inst{4-0} = Rb;
+}
+
+class LBI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b010011, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<6> addr;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = addr{5-3};  // Ra
+  let Inst{2-0} = addr{2-0};  // imm3u
+}
+
+class LHI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b010010, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<6> addr;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = addr{5-3};  // Ra
+  let Inst{2-0} = addr{2-0};  // imm3u
+}
+
+class LWI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b010000, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<6> addr;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = addr{5-3};  // Ra
+  let Inst{2-0} = addr{2-0};  // imm3u
+}
+
+class LWI450Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b011010, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> addr;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = addr{4-0};  // Ra
+}
+
+class MOV55Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst5BitOpcode<0b00000, outs, ins, asmstr, pattern> {
+  bits<5> Rt;
+  bits<5> Ra;
+  let Inst{9-5} = Rt;
+  let Inst{4-0} = Ra;
+}
+
+class MOVI55Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst5BitOpcode<0b00001, outs, ins, asmstr, pattern> {
+  bits<5> Rt;
+  bits<5> imm;
+  let Inst{9-5} = Rt;
+  let Inst{4-0} = imm;
+}
+
+class RET5Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst10BitOpcode<0b1011101100, outs, ins, asmstr, pattern> {
+  let Inst{4-0} = 30;  // LP register
+}
+
+class SBI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b010111, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<6> addr;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = addr{5-3};  // Ra
+  let Inst{2-0} = addr{2-0};  // imm3u
+}
+
+class SHI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b010110, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<6> addr;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = addr{5-3};  // Ra
+  let Inst{2-0} = addr{2-0};  // imm3u
+}
+
+class SWI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b010100, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<6> addr;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = addr{5-3};  // Ra
+  let Inst{2-0} = addr{2-0};  // imm3u
+}
+
+class BFMI333Form<dag outs, dag ins, string asmstr, list<dag> pattern,
+		  bits<3> subop_encode>
+  : 16BitInst6BitOpcode<0b001011, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = subop_encode;
+}
+
+class SLLI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001010, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  bits<3> imm;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = imm;
+}
+
+class SRAI45Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001000, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> imm;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = imm;
+}
+
+class SRLI45Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001001, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> imm;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = imm;
+}
+
+class SUB333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001101, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  bits<3> Rb;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = Rb;
+}
+
+class SUB45Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b000101, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> Rb;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = Rb;
+}
+
+class SUBI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b001111, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  bits<3> imm;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = imm;
+}
+
+class SUBI45Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b000111, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> imm;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = imm;
+}
+
+class SWI450Form<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : 16BitInst6BitOpcode<0b011011, outs, ins, asmstr, pattern> {
+  bits<4> Rt;
+  bits<5> addr;
+  let Inst{8-5} = Rt;
+  let Inst{4-0} = addr{4-0};  // Ra
+}
+
+class MISC33Form<dag outs, dag ins, string asmstr, list<dag> pattern,
+		 bits<3> subop_encode>
+  : 16BitInst6BitOpcode<0b111111, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = subop_encode;
+}
+
+class XWI37Form<dag outs, dag ins, string asmstr, list<dag> pattern,
+		  bit store>
+  : 16BitInst4BitOpcode<0b0111, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<7> addr;
+  let Inst{10-8} = Rt;
+  let Inst{7} = store;
+  let Inst{6-0} = addr;
+}
+
+class XWI37SPForm<dag outs, dag ins, string asmstr, list<dag> pattern,
+		  bit store>
+  : 16BitInst4BitOpcode<0b1110, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<7> addr;
+  let Inst{10-8} = Rt;
+  let Inst{7} = store;
+  let Inst{6-0} = addr;
+}
+
+// NDS16Pat - Same as Pat<>, but requires has 16-bit ISA support.
+class NDS16Pat<dag pattern, dag result> : Pat<pattern, result> {
+  list<Predicate> Predicates = [Has16Bit];
+}