Index: lib/Target/NDS32/CMakeLists.txt
===================================================================
--- lib/Target/NDS32/CMakeLists.txt
+++ lib/Target/NDS32/CMakeLists.txt
@@ -1,3 +1,11 @@
+set(LLVM_TARGET_DEFINITIONS NDS32.td)
+
+tablegen(LLVM NDS32GenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM NDS32GenCallingConv.inc -gen-callingconv)
+
+add_public_tablegen_target(NDS32CommonTableGen)
+
+
 add_llvm_target(NDS32CodeGen
   NDS32TargetMachine.cpp
   )
Index: lib/Target/NDS32/NDS32.td
===================================================================
--- /dev/null
+++ lib/Target/NDS32/NDS32.td
@@ -0,0 +1,44 @@
+//===-- NDS32.td - Describe the NDS32 Target Machine -----*- tablegen -*---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This is the top level entry point for the NDS32 target.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// Subtarget Features.
+//===----------------------------------------------------------------------===//
+
+def FeatureNo16Bit : SubtargetFeature<"no-16bit", "No16Bit", "true",
+                                      "Disable generate 16-bit ISA">;
+
+
+//===----------------------------------------------------------------------===//
+// NDS32 supported processors.
+//===----------------------------------------------------------------------===//
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic",         []>;
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "NDS32RegisterInfo.td"
+
+//===----------------------------------------------------------------------===//
+// Calling Convention Description
+//===----------------------------------------------------------------------===//
+
+include "NDS32CallingConv.td"
Index: lib/Target/NDS32/NDS32CallingConv.td
===================================================================
--- /dev/null
+++ lib/Target/NDS32/NDS32CallingConv.td
@@ -0,0 +1,74 @@
+//==- NDS32CallingConv.td - Calling Conventions for NDS32 -*- tablegen -*---==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This describes the calling conventions for NDS32 architecture.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// NDS32 Return Value Calling Convention
+//===----------------------------------------------------------------------===//
+def RetCC_NDS32_SoftFloat : CallingConv<[
+  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
+  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>,
+
+  CCIfType<[f32], CCBitConvertToType<i32>>
+]>;
+
+def RetCC_NDS32 : CallingConv<[
+  CCDelegateTo<RetCC_NDS32_SoftFloat>
+]>;
+
+//===----------------------------------------------------------------------===//
+// NDS32 Argument Calling Conventions
+//===----------------------------------------------------------------------===//
+
+/// CCIfAlign - Match of the original alignment of the arg
+class CCIfAlign<string Align, CCAction A>:
+  CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
+
+class CCIfNotAlign<string Align, CCAction A>:
+  CCIf<!strconcat("ArgFlags.getOrigAlign() != ", Align), A>;
+
+def CC_NDS32_SoftFloat : CallingConv<[
+  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+
+  // Pass by value if the byval attribute is given
+  CCIfByVal<CCPassByVal<4, 4>>,
+
+  // The first to sixth argument are passed with register R0 ~ R5.
+  // Not align to 8 byte mean it's i32 or f32
+  CCIfType<[i32], CCIfNotAlign<"8", CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>>,
+  // Align to 8 byte mean it's i64 or f64, it's passed in even pairs of GPRs
+  // need to pad R1/R3 if assign to R2/R4.
+  CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2, R4],
+                                                         [R0, R1, R3]>>>,
+
+  // If a part of argument assign to stack, shadow the argument registers.
+  // To avoid a double argument assign to stack and register in the same time.
+  CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2,
+                                                                  R3, R4, R5]>>>,
+
+  CCIfType<[f32], CCBitConvertToType<i32>>,
+  CCIfType<[i64, f64], CCAssignToRegWithShadow<[R0, R2, R4], [R1, R3, R5]>>,
+
+  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
+  CCIfType<[i64, f64], CCAssignToStack<8, 8>>
+]>;
+
+def CC_NDS32 : CallingConv<[
+  CCDelegateTo<CC_NDS32_SoftFloat>
+]>;
+
+
+//===----------------------------------------------------------------------===//
+// Callee-saved register lists.
+//===----------------------------------------------------------------------===//
+
+// Callee save registers for V3 Architecture
+def CSR_V3 : CalleeSavedRegs<(add LP, FP, (sequence "R%u", 14, 6))>;
Index: lib/Target/NDS32/NDS32RegisterInfo.td
===================================================================
--- /dev/null
+++ lib/Target/NDS32/NDS32RegisterInfo.td
@@ -0,0 +1,95 @@
+//===-- NDS32RegisterInfo.td - NDS32 Register defs -------*- tablegen -*---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the NDS32 register file
+//===----------------------------------------------------------------------===//
+
+class NDS32Reg<bits<16> Enc, string n> : Register<n> {
+  let HWEncoding = Enc;
+  let Namespace = "NDS32";
+}
+
+class Unallocatable {
+  bit isAllocatable = 0;
+}
+
+
+//===----------------------------------------------------------------------===//
+//  Registers
+//===----------------------------------------------------------------------===//
+
+def R0  : NDS32Reg<0,  "r0">,  DwarfRegNum<[0]>;
+def R1  : NDS32Reg<1,  "r1">,  DwarfRegNum<[1]>;
+def R2  : NDS32Reg<2,  "r2">,  DwarfRegNum<[2]>;
+def R3  : NDS32Reg<3,  "r3">,  DwarfRegNum<[3]>;
+def R4  : NDS32Reg<4,  "r4">,  DwarfRegNum<[4]>;
+def R5  : NDS32Reg<5,  "r5">,  DwarfRegNum<[5]>;
+def R6  : NDS32Reg<6,  "r6">,  DwarfRegNum<[6]>;
+def R7  : NDS32Reg<7,  "r7">,  DwarfRegNum<[7]>;
+def R8  : NDS32Reg<8,  "r8">,  DwarfRegNum<[8]>;
+def R9  : NDS32Reg<9,  "r9">,  DwarfRegNum<[9]>;
+def R10 : NDS32Reg<10, "r10">, DwarfRegNum<[10]>;
+def R11 : NDS32Reg<11, "r11">, DwarfRegNum<[11]>;
+def R12 : NDS32Reg<12, "r12">, DwarfRegNum<[12]>;
+def R13 : NDS32Reg<13, "r13">, DwarfRegNum<[13]>;
+def R14 : NDS32Reg<14, "r14">, DwarfRegNum<[14]>;
+def R15 : NDS32Reg<15, "r15">, DwarfRegNum<[15]>;
+def R16 : NDS32Reg<16, "r16">, DwarfRegNum<[16]>;
+def R17 : NDS32Reg<17, "r17">, DwarfRegNum<[17]>;
+def R18 : NDS32Reg<18, "r18">, DwarfRegNum<[18]>;
+def R19 : NDS32Reg<19, "r19">, DwarfRegNum<[19]>;
+def R20 : NDS32Reg<20, "r20">, DwarfRegNum<[20]>;
+def R21 : NDS32Reg<21, "r21">, DwarfRegNum<[21]>;
+def R22 : NDS32Reg<22, "r22">, DwarfRegNum<[22]>;
+def R23 : NDS32Reg<23, "r23">, DwarfRegNum<[23]>;
+def R24 : NDS32Reg<24, "r24">, DwarfRegNum<[24]>;
+def R25 : NDS32Reg<25, "r25">, DwarfRegNum<[25]>;
+def R26 : NDS32Reg<26, "r26">, DwarfRegNum<[26]>;
+def R27 : NDS32Reg<27, "r27">, DwarfRegNum<[27]>;
+def FP  : NDS32Reg<28, "fp">,  DwarfRegNum<[28]>;
+def GP  : NDS32Reg<29, "gp">,  DwarfRegNum<[29]>;
+def LP  : NDS32Reg<30, "lp">,  DwarfRegNum<[30]>;
+def SP  : NDS32Reg<31, "sp">,  DwarfRegNum<[31]>;
+
+
+def GPR : RegisterClass<"NDS32", [i32], 32,
+  (add  (sequence "R%u", 0, 27),
+   FP, GP, LP, SP)>;
+
+// The low registers for 16 bit instruction, R0-R7.
+def lGPR : RegisterClass<"NDS32", [i32], 32,
+  (add  (sequence "R%u", 0, 7))>;
+
+// The middle registers for 16 bit instruction, R0-R11, R16-R19
+def mGPR : RegisterClass<"NDS32", [i32], 32,
+  (add  (sequence "R%u", 0, 11),
+        (sequence "R%u", 16, 19))>;
+
+// The high registers R12-R15, R20-R31
+def hGPR : RegisterClass<"NDS32", [i32], 32, (sub GPR, mGPR)>;
+
+def FPReg : RegisterClass<"NDS32", [i32], 32, (add FP)>, Unallocatable;
+def SPReg : RegisterClass<"NDS32", [i32], 32, (add SP)>, Unallocatable;
+
+//-----------------------
+// Register Operands.
+
+class NDS32AsmRegOperand : AsmOperandClass {
+  let ParserMethod = "parseAnyRegister";
+}
+
+def GPRAsmOperand : NDS32AsmRegOperand {
+  let Name = "GPRAsmReg";
+  let PredicateMethod = "isGPRAsmReg";
+}
+
+def GPROpnd : RegisterOperand<GPR> {
+  let ParserMatchClass = GPRAsmOperand;
+}