Index: CMakeLists.txt =================================================================== --- CMakeLists.txt +++ CMakeLists.txt @@ -331,6 +331,7 @@ Mips MSP430 NVPTX + NDS32 PowerPC RISCV Sparc Index: docs/CompilerWriterInfo.rst =================================================================== --- docs/CompilerWriterInfo.rst +++ docs/CompilerWriterInfo.rst @@ -114,6 +114,11 @@ * `The XMOS XS1 Architecture (ISA) `_ * `Tools Development Guide (includes ABI) `_ +NDS32 +------ +* `AndeStar ISA Manual (V3 ISA) `_ +* NOTE: This is an experimental porting of LLVM for AndeStar V3 ISA (NDS32 V3) of Andes Technology Corporation. Function-wise, correct code sequence is generated and it has passed key test suites. Performance-wise, there is NO target-specific optimization yet. + Hexagon ------- Index: lib/Target/LLVMBuild.txt =================================================================== --- lib/Target/LLVMBuild.txt +++ lib/Target/LLVMBuild.txt @@ -28,6 +28,7 @@ Hexagon MSP430 NVPTX + NDS32 Mips PowerPC RISCV Index: lib/Target/NDS32/CMakeLists.txt =================================================================== --- /dev/null +++ lib/Target/NDS32/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_target(NDS32CodeGen + NDS32TargetMachine.cpp + ) Index: lib/Target/NDS32/LLVMBuild.txt =================================================================== --- /dev/null +++ lib/Target/NDS32/LLVMBuild.txt @@ -0,0 +1,31 @@ +;===- ./lib/Target/NDS32/LLVMBuild.txt ------------------------*- Conf -*---===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[common] +subdirectories = TargetInfo + +[component_0] +type = TargetGroup +name = NDS32 +parent = Target + +[component_1] +type = Library +name = NDS32CodeGen +parent = NDS32 +required_libraries = CodeGen Core NDS32Info Support Target +add_to_library_groups = NDS32 Index: lib/Target/NDS32/NDS32TargetMachine.h =================================================================== --- /dev/null +++ lib/Target/NDS32/NDS32TargetMachine.h @@ -0,0 +1,53 @@ +//===-- NDS32TargetMachine.h - Define TargetMachine for NDS32 -*- C++ -*---===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the NDS32 specific subclass of TargetMachine. +// +//===----------------------------------------------------------------------===// + + +#ifndef LLVM_LIB_TARGET_NDS32_NDS32TARGETMACHINE_H +#define LLVM_LIB_TARGET_NDS32_NDS32TARGETMACHINE_H + +#include "NDS32Subtarget.h" +#include "llvm/Target/TargetFrameLowering.h" +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + +/// NDS32TargetMachine +/// +class NDS32TargetMachine : public LLVMTargetMachine { + +protected: + std::unique_ptr TLOF; + NDS32Subtarget Subtarget; + mutable StringMap> SubtargetMap; + + +public: + NDS32TargetMachine(const Target &T, const Triple &TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Optional RM, CodeModel::Model CM, + CodeGenOpt::Level OL); + ~NDS32TargetMachine() override; + + const NDS32Subtarget *getSubtargetImpl() const { return &Subtarget; } + const NDS32Subtarget *getSubtargetImpl(const Function &F) const override; + + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } +}; // NDS32TargetMachine. + +} // end namespace llvm + +#endif Index: lib/Target/NDS32/NDS32TargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/NDS32/NDS32TargetMachine.cpp @@ -0,0 +1,122 @@ +//===-- NDS32TargetMachine.cpp - Define TargetMachine for NDS32 -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Top-level implementation for the NDS32 target. +// +//===----------------------------------------------------------------------===// + +#include "NDS32TargetMachine.h" +#include "NDS32.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +extern "C" void LLVMInitializeNDS32Target() { + // Register the target. + RegisterTargetMachine X(TheNDS32Target); +} + +static Reloc::Model getEffectiveRelocModel(Optional RM) { + if (!RM.hasValue()) + return Reloc::Static; + return *RM; +} + +static std::string computeDataLayout(const Triple &TT, StringRef CPU, + const TargetOptions &Options, + bool isLittle) { + std::string Ret = ""; + + if (isLittle) + // Little endian. + Ret += "e"; + else + // Big endian. + Ret += "E"; + + //ELF mangling of names is enabled + Ret += "-m:e"; + + // Pointers are 32 bits and aligned to 32 bits. + Ret += "-p:32:32"; + + // 64 bit integers with natural alignment. + Ret += "-i64:64"; + + // Try to align aggregates to 32 bits + Ret += "-a:0:32"; + + // Integer registers are 32 bits. + Ret += "-n32"; + + // The stack is 64 bit aligned + Ret += "-S64"; + + return Ret; +} + +NDS32TargetMachine::NDS32TargetMachine(const Target &T, const Triple &TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Optional RM, + CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, true), + TT, CPU, FS, Options, getEffectiveRelocModel(RM), + CM, OL), + TLOF(make_unique()), + Subtarget(TT, CPU, FS, *this) { + initAsmInfo(); +} + +NDS32TargetMachine::~NDS32TargetMachine() {} + +const NDS32Subtarget * +NDS32TargetMachine::getSubtargetImpl(const Function &F) const { + Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute FSAttr = F.getFnAttribute("target-features"); + + std::string CPU = !CPUAttr.hasAttribute(Attribute::None) + ? CPUAttr.getValueAsString().str() + : TargetCPU; + std::string FS = !FSAttr.hasAttribute(Attribute::None) + ? FSAttr.getValueAsString().str() + : TargetFS; + + auto &I = SubtargetMap[CPU + FS]; + if (!I) { + // This needs to be done before we create a new subtarget since any + // creation will depend on the TM and the code generation flags on the + // function that reside in TargetOptions. + resetTargetOptions(F); + I = llvm::make_unique(TargetTriple, CPU, FS, *this); + } + return I.get(); +} + +namespace { +/// NDS32 Code Generator Pass Configuration Options. +class NDS32PassConfig : public TargetPassConfig { +public: + NDS32PassConfig(NDS32TargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + NDS32TargetMachine &getNDS32TargetMachine() const { + return getTM(); + } +}; +} // namespace + +TargetPassConfig *NDS32TargetMachine::createPassConfig(PassManagerBase &PM) { + return new NDS32PassConfig(this, PM); +}