Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/MipsABIInfo.h" #include "MipsTargetStreamer.h" #include "InstPrinter/MipsInstPrinter.h" #include "MipsELFStreamer.h" @@ -685,6 +686,17 @@ // issues as well. unsigned EFlags = MCA.getELFHeaderEFlags(); + // FIXME: Fix a dependency issue by instantiating the ABI object to some + // default based off the triple. The triple doesn't describe the target + // fully, but any external user of the API that uses the MCTargetStreamer + // would otherwise crash on assertion failure. + + ABI = MipsABIInfo( + STI.getTargetTriple().getArch() == Triple::ArchType::mipsel || + STI.getTargetTriple().getArch() == Triple::ArchType::mips + ? MipsABIInfo::O32() + : MipsABIInfo::N64()); + // Architecture if (Features[Mips::FeatureMips64r6]) EFlags |= ELF::EF_MIPS_ARCH_64R6; Index: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp +++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp @@ -3377,8 +3377,12 @@ DebugLoc DL = MI.getDebugLoc(); unsigned Wd = MI.getOperand(0).getReg(); unsigned Fs = MI.getOperand(1).getReg(); - unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); - unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + unsigned Wt1 = RegInfo.createVirtualRegister( + Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass + : &Mips::MSA128WEvensRegClass); + unsigned Wt2 = RegInfo.createVirtualRegister( + Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass + : &Mips::MSA128WEvensRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)