Index: ../tunkClang/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- ../tunkClang/lib/Target/X86/X86ISelLowering.cpp
+++ ../tunkClang/lib/Target/X86/X86ISelLowering.cpp
@@ -16843,6 +16843,35 @@
   return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
 }
 
+static SDValue getSelectMask(SDValue Cmp, SelectionDAG &DAG, MVT DestVT) {
+  SDLoc DL(Cmp);
+  SDValue Neg;
+  unsigned int CmpSz = Cmp.getSimpleValueType().getSizeInBits();
+  if (CmpSz > DestVT.getSizeInBits())
+    Neg = DAG.getNode(ISD::TRUNCATE, DL, DestVT, Cmp);
+  else if (CmpSz < DestVT.getSizeInBits())
+    Neg = DAG.getNode(ISD::AND, DL, DestVT,
+        DAG.getNode(ISD::ANY_EXTEND, DL, DestVT, Cmp.getOperand(0)), DAG.getConstant(1, DL, DestVT));
+  else
+    Neg = Cmp;
+  return DAG.getNode(ISD::SUB, DL, DestVT, DAG.getConstant(0, DL, DestVT), Neg);
+}
+
+// Return true if Op2 is XOR or OR operator and one of its operands
+// is equal to Op1 
+// ( a , a op b) || ( b , a op b)
+static bool isOrXorPattern(SDValue Op1, SDValue Op2, SDValue &Src1,
+                           SDValue &Src2, unsigned int &OpCode) {
+  if ((Op2.getOpcode() == ISD::XOR || Op2.getOpcode() == ISD::OR) &&
+      (Op2.getOperand(0) == Op1 || Op2.getOperand(1) == Op1)) {
+    OpCode = Op2.getOpcode();
+    Src1 = Op2.getOperand(0) == Op1 ? Op2.getOperand(1) : Op2.getOperand(0);
+    Src2 = Op1;
+    return true;
+  }
+  return false;
+}
+
 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   bool AddTest = true;
   SDValue Cond  = Op.getOperand(0);
@@ -16960,12 +16989,14 @@
   // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
   // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
   // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
+  // (select (and (x & 0x1) == 0), (z ^ y) , y ) -> (-(and (x & 0x1)) & z ) ^ y
+  // (select (and (x & 0x1) == 0), (z | y) , y ) -> (-(and (x & 0x1)) & z ) | y
   if (Cond.getOpcode() == X86ISD::SETCC &&
       Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
       isNullConstant(Cond.getOperand(1).getOperand(1))) {
     SDValue Cmp = Cond.getOperand(1);
-
-    unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
+    unsigned CondCode =
+        cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
 
     if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
         (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
@@ -17002,6 +17033,19 @@
       if (!isNullConstant(Op2))
         Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
       return Res;
+    } else if (!Subtarget.hasCMov() &&
+               CondCode == X86::COND_E &&
+               Cmp.getOperand(0).getOpcode() == ISD::AND &&
+               isOneConstant(Cmp.getOperand(0).getOperand(1))) {
+      SDValue CmpOp0 = Cmp.getOperand(0);
+      unsigned int OpCode;
+      SDValue Src1, Src2;
+      if (isOrXorPattern(Op2, Op1, Src1, Src2, OpCode) ||
+          isOrXorPattern(Op1, Op2, Src1, Src2, OpCode)) {
+        SDValue Mask = getSelectMask(CmpOp0, DAG, VT); // -(and (x & 0x1))
+        SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
+        return DAG.getNode(OpCode, DL, VT, And, Src2); // And Op y
+      }
     }
   }
 
Index: ../tunkClang/test/CodeGen/X86/select.ll
===================================================================
--- ../tunkClang/test/CodeGen/X86/select.ll
+++ ../tunkClang/test/CodeGen/X86/select.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=atom    | FileCheck %s --check-prefix=CHECK --check-prefix=ATOM
+; RUN: llc < %s -mtriple=i386-intel-elfiamcu                 | FileCheck %s --check-prefix=MCU
 
 ; PR5757
 %0 = type { i64, i32 }
@@ -635,3 +636,59 @@
   %B122 = fadd float %Sl59, undef
   ret void
 }
+
+define i16 @select_xor(i16 %A, i8 %cond) {
+; CHECK-LABEL: select_xor:
+; MCU:    andl    $1, %edx
+; MCU-NEXT:    negl    %edx
+; MCU-NEXT:    andl    $34, %edx
+; MCU-NEXT:    xorl    %edx, %eax
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = xor i16 %A, 34
+ %1 = select i1 %cmp10, i16 %A, i16 %0
+ ret i16 %1
+}
+
+define i16 @select_xor_1(i16 %A, i8 %cond) {
+; CHECK-LABEL: select_xor_1:
+; MCU:    andl    $1, %edx
+; MCU-NEXT:    negl    %edx
+; MCU-NEXT:    andl    $43, %edx
+; MCU-NEXT:    xorl    %edx, %eax
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = xor i16 %A, 43
+ %1 = select i1 %cmp10, i16 %0, i16 %A
+ ret i16 %1
+}
+
+define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
+; CHECK-LABEL: select_xor_2:
+; MCU:    andl $1, %ecx
+; MCU-NEXT:    negl %ecx
+; MCU-NEXT:    andl %edx, %ecx
+; MCU-NEXT:    xorl %ecx, %eax
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = xor i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
+define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
+; CHECK-LABEL: select_or:
+; MCU:    andl $1, %ecx
+; MCU-NEXT:    negl %ecx
+; MCU-NEXT:    andl %edx, %ecx
+; MCU-NEXT:    orl %ecx, %eax
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = or i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}