Index: lib/Target/X86/X86.td
===================================================================
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -209,9 +209,9 @@
 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
-def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
+def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
                                      "HasSlowDivide64", "true",
-                                     "Use 16-bit divide for positive values less than 65536">;
+                                     "Use 32-bit divide for positive values less than 2^32">;
 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
                                      "PadShortFunctions", "true",
                                      "Pad short functions">;
@@ -461,6 +461,7 @@
   FeatureCMPXCHG16B,
   FeaturePOPCNT,
   FeatureAES,
+  FeatureSlowDivide64,
   FeaturePCLMUL,
   FeatureXSAVE,
   FeatureXSAVEOPT,
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -97,12 +97,12 @@
   const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
   setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
 
-  // Bypass expensive divides on Atom when compiling with O2.
+  // Bypass expensive divides and use cheaper ones.
   if (TM.getOptLevel() >= CodeGenOpt::Default) {
     if (Subtarget.hasSlowDivide32())
       addBypassSlowDiv(32, 8);
     if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
-      addBypassSlowDiv(64, 16);
+      addBypassSlowDiv(64, 32);
   }
 
   if (Subtarget.isTargetKnownWindowsMSVC() ||
Index: lib/Target/X86/X86Subtarget.h
===================================================================
--- lib/Target/X86/X86Subtarget.h
+++ lib/Target/X86/X86Subtarget.h
@@ -216,7 +216,7 @@
   /// 32-bit divisions and should be used when possible.
   bool HasSlowDivide32;
 
-  /// True if 16-bit divides are significantly faster than
+  /// True if 32-bit divides are significantly faster than
   /// 64-bit divisions and should be used when possible.
   bool HasSlowDivide64;
 
Index: test/CodeGen/X86/atom-bypass-slow-division-64.ll
===================================================================
--- test/CodeGen/X86/atom-bypass-slow-division-64.ll
+++ test/CodeGen/X86/atom-bypass-slow-division-64.ll
@@ -1,4 +1,6 @@
-; RUN: llc < %s -mcpu=atom -march=x86-64 | FileCheck %s
+; RUN: llc < %s -mcpu=atom       -march=x86-64 -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mcpu=silvermont -march=x86-64 -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mcpu=skylake    -march=x86-64 -asm-verbose=false | FileCheck %s
 
 target triple = "x86_64-unknown-linux-gnu"
 
@@ -7,12 +9,13 @@
 define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: Test_get_quotient:
 ; CHECK: movq %rdi, %rax
-; CHECK: orq %rsi, %rax
-; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
+; CHECK-DAG: movabsq $-4294967296, %rcx
+; CHECK-DAG: orq %rsi, %rax
+; CHECK: testq %rcx, %rax
+; CHECK: je
 ; CHECK: idivq
 ; CHECK: ret
-; CHECK: divw
+; CHECK: divl
 ; CHECK: ret
   %result = sdiv i64 %a, %b
   ret i64 %result
@@ -21,12 +24,13 @@
 define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: Test_get_remainder:
 ; CHECK: movq %rdi, %rax
-; CHECK: orq %rsi, %rax
-; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
+; CHECK-DAG: movabsq $-4294967296, %rcx
+; CHECK-DAG: orq %rsi, %rax
+; CHECK: testq %rcx, %rax
+; CHECK: je
 ; CHECK: idivq
 ; CHECK: ret
-; CHECK: divw
+; CHECK: divl
 ; CHECK: ret
   %result = srem i64 %a, %b
   ret i64 %result
@@ -35,13 +39,16 @@
 define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: Test_get_quotient_and_remainder:
 ; CHECK: movq %rdi, %rax
-; CHECK: orq %rsi, %rax
-; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
+; CHECK-DAG: movabsq $-4294967296, %rcx
+; CHECK-DAG: orq %rsi, %rax
+; CHECK: testq %rcx, %rax
+; CHECK: je
 ; CHECK: idivq
-; CHECK: divw
-; CHECK: addq
-; CHECK: ret
+; CHECK-NEXT: addq
+; CHECK-NEXT: retq
+; CHECK: divl
+; CHECK-NEXT: addq
+; CHECK-NEXT: retq
 ; CHECK-NOT: idivq
 ; CHECK-NOT: divw
   %resultdiv = sdiv i64 %a, %b
Index: test/CodeGen/X86/slow-div.ll
===================================================================
--- test/CodeGen/X86/slow-div.ll
+++ test/CodeGen/X86/slow-div.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivl-to-divb < %s | FileCheck -check-prefix=DIV32 %s
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivq-to-divw < %s | FileCheck -check-prefix=DIV64 %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivq-to-divl < %s | FileCheck -check-prefix=DIV64 %s
 
 define i32 @div32(i32 %a, i32 %b) {
 entry:
@@ -16,11 +16,12 @@
 define i64 @div64(i64 %a, i64 %b) {
 entry:
 ; DIV32-LABEL: div64:
-; DIV32-NOT: divw
+; DIV32-NOT: divl
 ; DIV64-LABEL: div64:
-; DIV64: orq %{{.*}}, [[REG:%[a-z]+]]
-; DIV64: testq   $-65536, [[REG]]
-; DIV64: divw
+; DIV64-DAG: movabsq $-4294967296, [[REGMSK:%[a-z]+]]
+; DIV64-DAG: orq %{{.*}}, [[REG:%[a-z]+]]
+; DIV64: testq [[REGMSK]], [[REG]]
+; DIV64: divl
   %div = sdiv i64 %a, %b
   ret i64 %div
 }