Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1710,7 +1710,7 @@
   EVT CCT = getSetCCResultType(NVT);
 
   // Hi part is always the same op
-  Hi = DAG.getNode(N->getOpcode(), DL, {NVT, NVT}, {LHSH, RHSH});
+  Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
 
   // We need to know whether to select Lo part that corresponds to 'winning'
   // Hi part or if Hi parts are equal.
@@ -1721,7 +1721,7 @@
   SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
 
   // Recursed Lo part if Hi parts are equal, this uses unsigned version
-  SDValue LoMinMax = DAG.getNode(LoOpc, DL, {NVT, NVT}, {LHSL, RHSL});
+  SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
 
   Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
 }
Index: test/CodeGen/AMDGPU/legalize-umax-bug.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/legalize-umax-bug.mir
@@ -0,0 +1,89 @@
+# RUN: llc -march=r600 -mcpu=cypress -start-after safe-stack %s -o /dev/null
+
+# Don't crash
+
+--- |
+  target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+
+  @func_37.foo = internal unnamed_addr addrspace(3) global [256 x i64] undef
+
+  define void @func_37() #0 {
+    %1 = call i32 @llvm.r600.read.local.size.y(), !range !0
+    %2 = call i32 @llvm.r600.read.local.size.z(), !range !0
+    %3 = call i32 @llvm.r600.read.tidig.x(), !range !0
+    %4 = call i32 @llvm.r600.read.tidig.y(), !range !0
+    %5 = call i32 @llvm.r600.read.tidig.z(), !range !0
+    %6 = mul nuw nsw i32 %1, %2
+    %7 = mul i32 %6, %3
+    %8 = mul nuw nsw i32 %4, %2
+    %9 = add i32 %7, %8
+    %10 = add i32 %9, %5
+    %11 = getelementptr inbounds [256 x i64], [256 x i64] addrspace(3)* @func_37.foo, i32 0, i32 %10
+    br label %bb9.preheader
+
+  bb9.preheader:                                    ; preds = %0
+    store i64 2, i64 addrspace(3)* %11
+    %.promoted = load i64, i64 addrspace(3)* %11
+    %12 = add i64 %.promoted, 1
+    br label %bb14
+
+  bb14:                                             ; preds = %bb14, %bb9.preheader
+    %_tmp17464 = icmp ult i64 undef, 4
+    %13 = xor i1 %_tmp17464, true
+    br i1 %13, label %bb11, label %bb14
+
+  bb11:                                             ; preds = %bb14
+    %14 = icmp ugt i64 %12, 4
+    %umax = select i1 %14, i64 %12, i64 4
+    store i64 %umax, i64* undef
+    ret void
+  }
+
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.r600.read.local.size.y() #1
+
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.r600.read.local.size.z() #1
+
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.r600.read.tidig.x() #1
+
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.r600.read.tidig.y() #1
+
+  ; Function Attrs: nounwind readnone
+  declare i32 @llvm.r600.read.tidig.z() #1
+
+  attributes #0 = { "target-cpu"="cypress" }
+  attributes #1 = { nounwind readnone }
+
+  !0 = !{i32 0, i32 2048}
+
+...
+---
+name:            func_37
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+body:             |
+  bb.0 (%ir-block.0):
+    RETURN
+...