Index: lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- lib/Target/ARM/ARMBaseInstrInfo.cpp +++ lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -164,33 +164,33 @@ // Can't encode it in a so_imm operand. This transformation will // add more than 1 instruction. Abandon! return nullptr; - UpdateMI = BuildMI(MF, MI.getDebugLoc(), - get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) - .addReg(BaseReg) - .addImm(Amt) - .addImm(Pred) - .addReg(0) - .addReg(0); + UpdateMI = + AddDefaultCC(BuildMI(MF, MI.getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + .addReg(BaseReg) + .addImm(Amt) + .addImm(Pred) + .addReg(0)); } else if (Amt != 0) { ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); - UpdateMI = BuildMI(MF, MI.getDebugLoc(), - get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) - .addReg(BaseReg) - .addReg(OffReg) - .addReg(0) - .addImm(SOOpc) - .addImm(Pred) - .addReg(0) - .addReg(0); + UpdateMI = + AddDefaultCC(BuildMI(MF, MI.getDebugLoc(), + get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) + .addReg(BaseReg) + .addReg(OffReg) + .addReg(0) + .addImm(SOOpc) + .addImm(Pred) + .addReg(0)); } else - UpdateMI = BuildMI(MF, MI.getDebugLoc(), - get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) - .addReg(BaseReg) - .addReg(OffReg) - .addImm(Pred) - .addReg(0) - .addReg(0); + UpdateMI = + AddDefaultCC(BuildMI(MF, MI.getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + .addReg(BaseReg) + .addReg(OffReg) + .addImm(Pred) + .addReg(0)); break; } case ARMII::AddrMode3 : { @@ -198,21 +198,21 @@ unsigned Amt = ARM_AM::getAM3Offset(OffImm); if (OffReg == 0) // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. - UpdateMI = BuildMI(MF, MI.getDebugLoc(), - get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) - .addReg(BaseReg) - .addImm(Amt) - .addImm(Pred) - .addReg(0) - .addReg(0); + UpdateMI = + AddDefaultCC(BuildMI(MF, MI.getDebugLoc(), + get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) + .addReg(BaseReg) + .addImm(Amt) + .addImm(Pred) + .addReg(0)); else - UpdateMI = BuildMI(MF, MI.getDebugLoc(), - get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) - .addReg(BaseReg) - .addReg(OffReg) - .addImm(Pred) - .addReg(0) - .addReg(0); + UpdateMI = + AddDefaultCC(BuildMI(MF, MI.getDebugLoc(), + get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) + .addReg(BaseReg) + .addReg(OffReg) + .addImm(Pred) + .addReg(0)); break; } } @@ -433,7 +433,7 @@ if (!FBB) { if (Cond.empty()) { // Unconditional branch? if (isThumb) - BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); + AddDefaultPred(BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB)); else BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); } else @@ -446,7 +446,7 @@ BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addOperand(Cond[1]); if (isThumb) - BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); + AddDefaultPred(BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB)); else BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); return 2; @@ -2010,10 +2010,11 @@ const ARMBaseInstrInfo &TII, unsigned MIFlags) { if (NumBytes == 0 && DestReg != BaseReg) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) - .addReg(BaseReg, RegState::Kill) - .addImm((unsigned)Pred).addReg(PredReg).addReg(0) - .setMIFlags(MIFlags); + AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) + .addReg(BaseReg, RegState::Kill) + .addImm((unsigned)Pred) + .addReg(PredReg)) + .setMIFlags(MIFlags); return; } @@ -2032,10 +2033,12 @@ // Build the new ADD / SUB. unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; - BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) - .addReg(BaseReg, RegState::Kill).addImm(ThisVal) - .addImm((unsigned)Pred).addReg(PredReg).addReg(0) - .setMIFlags(MIFlags); + AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) + .addReg(BaseReg, RegState::Kill) + .addImm(ThisVal) + .addImm((unsigned)Pred) + .addReg(PredReg)) + .setMIFlags(MIFlags); BaseReg = DestReg; } } Index: lib/Target/ARM/ARMConstantIslandPass.cpp =================================================================== --- lib/Target/ARM/ARMConstantIslandPass.cpp +++ lib/Target/ARM/ARMConstantIslandPass.cpp @@ -897,8 +897,7 @@ if (!isThumb) BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB); else - BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB) - .addImm(ARMCC::AL).addReg(0); + AddDefaultPred(BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)); ++NumSplit; // Update the CFG. All succs of OrigBB are now succs of NewBB. @@ -1296,8 +1295,8 @@ if (!isThumb) BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); else - BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB) - .addImm(ARMCC::AL).addReg(0); + AddDefaultPred( + BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)); unsigned MaxDisp = getUnconditionalBrDisp(UncondBr); ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr)); @@ -1681,8 +1680,8 @@ Br.MI = &MBB->back(); BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); if (isThumb) - BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB) - .addImm(ARMCC::AL).addReg(0); + AddDefaultPred( + BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)); else BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); @@ -2236,15 +2235,9 @@ // There doesn't seem to be meaningful DebugInfo available; this doesn't // correspond directly to anything in the source. if (isThumb2) - BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)) - .addMBB(BB) - .addImm(ARMCC::AL) - .addReg(0); + AddDefaultPred(BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB)); else - BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB)) - .addMBB(BB) - .addImm(ARMCC::AL) - .addReg(0); + AddDefaultPred(BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB)).addMBB(BB)); // Update internal data structures to account for the newly inserted MBB. MF->RenumberBlocks(NewBB); Index: lib/Target/ARM/ARMExpandPseudoInsts.cpp =================================================================== --- lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -696,8 +696,8 @@ HI16 = HI16.addImm(SOImmValV2); LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); - LO16.addImm(Pred).addReg(PredReg).addReg(0); - HI16.addImm(Pred).addReg(PredReg).addReg(0); + AddDefaultCC(LO16.addImm(Pred).addReg(PredReg)); + AddDefaultCC(HI16.addImm(Pred).addReg(PredReg)); TransferImpOps(MI, LO16, HI16); MI.eraseFromParent(); return; @@ -1026,7 +1026,7 @@ // Add the default predicate in Thumb mode. if (STI->isThumb()) - MIB.addImm(ARMCC::AL).addReg(0); + AddDefaultPred(MIB); } else if (RetOpcode == ARM::TCRETURNri) { BuildMI(MBB, MBBI, dl, TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)) @@ -1057,37 +1057,34 @@ case ARM::t2MOVCCr: case ARM::MOVCCr: { unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), - MI.getOperand(1).getReg()) - .addOperand(MI.getOperand(2)) - .addImm(MI.getOperand(3).getImm()) // 'pred' - .addOperand(MI.getOperand(4)) - .addReg(0); // 's' bit + AddDefaultCC(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), + MI.getOperand(1).getReg()) + .addOperand(MI.getOperand(2)) + .addImm(MI.getOperand(3).getImm()) // 'pred' + .addOperand(MI.getOperand(4))); MI.eraseFromParent(); return true; } case ARM::MOVCCsi: { - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), - (MI.getOperand(1).getReg())) - .addOperand(MI.getOperand(2)) - .addImm(MI.getOperand(3).getImm()) - .addImm(MI.getOperand(4).getImm()) // 'pred' - .addOperand(MI.getOperand(5)) - .addReg(0); // 's' bit + AddDefaultCC(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), + (MI.getOperand(1).getReg())) + .addOperand(MI.getOperand(2)) + .addImm(MI.getOperand(3).getImm()) + .addImm(MI.getOperand(4).getImm()) // 'pred' + .addOperand(MI.getOperand(5))); MI.eraseFromParent(); return true; } case ARM::MOVCCsr: { - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), - (MI.getOperand(1).getReg())) - .addOperand(MI.getOperand(2)) - .addOperand(MI.getOperand(3)) - .addImm(MI.getOperand(4).getImm()) - .addImm(MI.getOperand(5).getImm()) // 'pred' - .addOperand(MI.getOperand(6)) - .addReg(0); // 's' bit + AddDefaultCC(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), + (MI.getOperand(1).getReg())) + .addOperand(MI.getOperand(2)) + .addOperand(MI.getOperand(3)) + .addImm(MI.getOperand(4).getImm()) + .addImm(MI.getOperand(5).getImm()) // 'pred' + .addOperand(MI.getOperand(6))); MI.eraseFromParent(); return true; @@ -1106,12 +1103,11 @@ case ARM::t2MOVCCi: case ARM::MOVCCi: { unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), - MI.getOperand(1).getReg()) - .addImm(MI.getOperand(2).getImm()) - .addImm(MI.getOperand(3).getImm()) // 'pred' - .addOperand(MI.getOperand(4)) - .addReg(0); // 's' bit + AddDefaultCC(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), + MI.getOperand(1).getReg()) + .addImm(MI.getOperand(2).getImm()) + .addImm(MI.getOperand(3).getImm()) // 'pred' + .addOperand(MI.getOperand(4))); MI.eraseFromParent(); return true; @@ -1119,12 +1115,11 @@ case ARM::t2MVNCCi: case ARM::MVNCCi: { unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), - MI.getOperand(1).getReg()) - .addImm(MI.getOperand(2).getImm()) - .addImm(MI.getOperand(3).getImm()) // 'pred' - .addOperand(MI.getOperand(4)) - .addReg(0); // 's' bit + AddDefaultCC(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), + MI.getOperand(1).getReg()) + .addImm(MI.getOperand(2).getImm()) + .addImm(MI.getOperand(3).getImm()) // 'pred' + .addOperand(MI.getOperand(4))); MI.eraseFromParent(); return true; @@ -1141,13 +1136,12 @@ case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; default: llvm_unreachable("unexpeced conditional move"); } - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), - MI.getOperand(1).getReg()) - .addOperand(MI.getOperand(2)) - .addImm(MI.getOperand(3).getImm()) - .addImm(MI.getOperand(4).getImm()) // 'pred' - .addOperand(MI.getOperand(5)) - .addReg(0); // 's' bit + AddDefaultCC(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), + MI.getOperand(1).getReg()) + .addOperand(MI.getOperand(2)) + .addImm(MI.getOperand(3).getImm()) + .addImm(MI.getOperand(4).getImm()) // 'pred' + .addOperand(MI.getOperand(5))); MI.eraseFromParent(); return true; } @@ -1213,12 +1207,11 @@ } case ARM::RRX: { // This encodes as "MOVs Rd, Rm, rrx - MachineInstrBuilder MIB = - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), - MI.getOperand(0).getReg()) - .addOperand(MI.getOperand(1)) - .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) - .addReg(0); + MachineInstrBuilder MIB = AddDefaultCC(AddDefaultPred( + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), + MI.getOperand(0).getReg()) + .addOperand(MI.getOperand(1)) + .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))); TransferImpOps(MI, MIB, MIB); MI.eraseFromParent(); return true; @@ -1227,10 +1220,9 @@ case ARM::TPsoft: { MachineInstrBuilder MIB; if (Opcode == ARM::tTPsoft) - MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get( ARM::tBL)) - .addImm((unsigned)ARMCC::AL).addReg(0) - .addExternalSymbol("__aeabi_read_tp", 0); + MIB = AddDefaultPred( + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL))) + .addExternalSymbol("__aeabi_read_tp", 0); else MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get( ARM::BL)) Index: lib/Target/ARM/ARMFrameLowering.cpp =================================================================== --- lib/Target/ARM/ARMFrameLowering.cpp +++ lib/Target/ARM/ARMFrameLowering.cpp @@ -461,11 +461,10 @@ case CodeModel::Medium: case CodeModel::Default: case CodeModel::Kernel: - BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) - .addImm((unsigned)ARMCC::AL).addReg(0) - .addExternalSymbol("__chkstk") - .addReg(ARM::R4, RegState::Implicit) - .setMIFlags(MachineInstr::FrameSetup); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))) + .addExternalSymbol("__chkstk") + .addReg(ARM::R4, RegState::Implicit) + .setMIFlags(MachineInstr::FrameSetup); break; case CodeModel::Large: case CodeModel::JITDefault: @@ -473,11 +472,10 @@ .addExternalSymbol("__chkstk") .setMIFlags(MachineInstr::FrameSetup); - BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) - .addImm((unsigned)ARMCC::AL).addReg(0) - .addReg(ARM::R12, RegState::Kill) - .addReg(ARM::R4, RegState::Implicit) - .setMIFlags(MachineInstr::FrameSetup); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))) + .addReg(ARM::R12, RegState::Kill) + .addReg(ARM::R4, RegState::Implicit) + .setMIFlags(MachineInstr::FrameSetup); break; } @@ -675,10 +673,9 @@ // FIXME: Clarify FrameSetup flags here. if (RegInfo->hasBasePointer(MF)) { if (isARM) - BuildMI(MBB, MBBI, dl, - TII.get(ARM::MOVr), RegInfo->getBaseRegister()) - .addReg(ARM::SP) - .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); + AddDefaultCC(AddDefaultPred( + BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) + .addReg(ARM::SP))); else AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) @@ -764,8 +761,9 @@ } else { // Thumb2 or ARM. if (isARM) - BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) - .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); + AddDefaultCC( + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) + .addReg(FramePtr))); else AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) @@ -2109,8 +2107,8 @@ AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) .addReg(ARM::SP)); } else if (CompareStackPointer) { - AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) - .addReg(ARM::SP)).addReg(0); + AddDefaultCC(AddDefaultPred( + BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1).addReg(ARM::SP))); } // sub SR1, sp, #StackSize @@ -2119,8 +2117,10 @@ AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)) .addReg(ScratchReg1).addImm(AlignedStackSize)); } else if (!CompareStackPointer) { - AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) - .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0); + AddDefaultCC( + AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) + .addReg(ARM::SP) + .addImm(AlignedStackSize))); } if (Thumb && ST->isThumb1Only()) { @@ -2181,8 +2181,9 @@ AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)).addImm(AlignedStackSize)); } else { - AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) - .addImm(AlignedStackSize)).addReg(0); + AddDefaultCC( + AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) + .addImm(AlignedStackSize))); } // Pass second argument for the __morestack by Scratch Register #1. // The amount size of stack consumed to save function arguments. @@ -2191,9 +2192,9 @@ AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)) .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))); } else { - AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) - .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))) - .addReg(0); + AddDefaultCC(AddDefaultPred( + BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) + .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))); } // push {lr} - Save return address of this function. Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -8662,12 +8662,12 @@ case CodeModel::Medium: case CodeModel::Default: case CodeModel::Kernel: - BuildMI(*MBB, MI, DL, TII.get(ARM::tBL)) - .addImm((unsigned)ARMCC::AL).addReg(0) - .addExternalSymbol("__chkstk") - .addReg(ARM::R4, RegState::Implicit | RegState::Kill) - .addReg(ARM::R4, RegState::Implicit | RegState::Define) - .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead); + AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))) + .addExternalSymbol("__chkstk") + .addReg(ARM::R4, RegState::Implicit | RegState::Kill) + .addReg(ARM::R4, RegState::Implicit | RegState::Define) + .addReg(ARM::R12, + RegState::Implicit | RegState::Define | RegState::Dead); break; case CodeModel::Large: case CodeModel::JITDefault: { @@ -8676,12 +8676,12 @@ BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg) .addExternalSymbol("__chkstk"); - BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr)) - .addImm((unsigned)ARMCC::AL).addReg(0) - .addReg(Reg, RegState::Kill) - .addReg(ARM::R4, RegState::Implicit | RegState::Kill) - .addReg(ARM::R4, RegState::Implicit | RegState::Define) - .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead); + AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))) + .addReg(Reg, RegState::Kill) + .addReg(ARM::R4, RegState::Implicit | RegState::Kill) + .addReg(ARM::R4, RegState::Implicit | RegState::Define) + .addReg(ARM::R12, + RegState::Implicit | RegState::Define | RegState::Dead); break; } } @@ -8972,10 +8972,11 @@ // insert rsbri in RSBBB // Note: BCC and rsbri will be converted into predicated rsbmi // by if-conversion pass - BuildMI(*RSBBB, RSBBB->begin(), dl, - TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) - .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0) - .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); + AddDefaultCC(AddDefaultPred( + BuildMI(*RSBBB, RSBBB->begin(), dl, + TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) + .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0) + .addImm(0))); // insert PHI in SinkBB, // reuse ABSDstReg to not change uses of ABS instruction Index: lib/Target/ARM/ThumbRegisterInfo.cpp =================================================================== --- lib/Target/ARM/ThumbRegisterInfo.cpp +++ lib/Target/ARM/ThumbRegisterInfo.cpp @@ -92,10 +92,10 @@ Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val); unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); - BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) - .addReg(DestReg, getDefRegState(true), SubIdx) - .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0) - .setMIFlags(MIFlags); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) + .addReg(DestReg, getDefRegState(true), SubIdx) + .addConstantPoolIndex(Idx)) + .setMIFlags(MIFlags); } /// emitLoadConstPool - Emits a load from constpool to materialize the