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Differential D27929

AMDGPU: Allow 16-bit types in inline asm constraints
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Authored by arsenm on Dec 19 2016, 10:16 AM.

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• tstellarAMD

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arsenm updated this revision to Diff 81972.Dec 19 2016, 10:16 AM
arsenm retitled this revision from to AMDGPU: Allow 16-bit types in inline asm constraints.
arsenm updated this object.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptDec 19 2016, 10:16 AM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript
• tstellarAMD accepted this revision.Dec 19 2016, 2:20 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Dec 19 2016, 2:20 PM
arsenm closed this revision.Dec 20 2016, 11:16 AM

r290193

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
42 lines

Diff 81972

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 4,510 Lines • ▼ Show 20 LinesSITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Constraint.size() == 1) { if (Constraint.size() == 1) {
switch (Constraint[0]) { switch (Constraint[0]) {
case 's': case 's':
case 'r': case 'r':
switch (VT.getSizeInBits()) { switch (VT.getSizeInBits()) {
default: default:
return std::make_pair(0U, nullptr); return std::make_pair(0U, nullptr);
case 32: case 32:
case 16:
return std::make_pair(0U, &AMDGPU::SReg_32_XM0RegClass); return std::make_pair(0U, &AMDGPU::SReg_32_XM0RegClass);
case 64: case 64:
return std::make_pair(0U, &AMDGPU::SGPR_64RegClass); return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
case 128: case 128:
return std::make_pair(0U, &AMDGPU::SReg_128RegClass); return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
case 256: case 256:
return std::make_pair(0U, &AMDGPU::SReg_256RegClass); return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
} }
case 'v': case 'v':
switch (VT.getSizeInBits()) { switch (VT.getSizeInBits()) {
default: default:
return std::make_pair(0U, nullptr); return std::make_pair(0U, nullptr);
case 32: case 32:
case 16:
return std::make_pair(0U, &AMDGPU::VGPR_32RegClass); return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
case 64: case 64:
return std::make_pair(0U, &AMDGPU::VReg_64RegClass); return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
case 96: case 96:
return std::make_pair(0U, &AMDGPU::VReg_96RegClass); return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
case 128: case 128:
return std::make_pair(0U, &AMDGPU::VReg_128RegClass); return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
case 256: case 256:
Show All 37 Lines

test/CodeGen/AMDGPU/inlineasm-16.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: not llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s
; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s
; GCN-LABEL: {{^}}s_input_output_i16:
; SICI: error: couldn't allocate output register for constraint 's'
; SICI: error: couldn't allocate input reg for constraint 's'
define void @s_input_output_i16() #0 {
%v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
ret void
}
; GCN-LABEL: {{^}}v_input_output_i16:
; SICI: error: couldn't allocate output register for constraint 'v'
; SICI: error: couldn't allocate input reg for constraint 'v'
define void @v_input_output_i16() #0 {
%v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
tail call void asm sideeffect "; use $0", "v"(i16 %v)
ret void
}
; GCN-LABEL: {{^}}s_input_output_f16:
; SICI: error: couldn't allocate output register for constraint 's'
; SICI: error: couldn't allocate input reg for constraint 's'
define void @s_input_output_f16() #0 {
%v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"()
tail call void asm sideeffect "; use $0", "s"(half %v)
ret void
}
; GCN-LABEL: {{^}}v_input_output_f16:
; SICI: error: couldn't allocate output register for constraint 'v'
; SICI: error: couldn't allocate input reg for constraint 'v'
define void @v_input_output_f16() #0 {
%v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"()
tail call void asm sideeffect "; use $0", "v"(half %v)
ret void
}
attributes #0 = { nounwind }