Index: lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP1Instructions.td +++ lib/Target/AMDGPU/VOP1Instructions.td @@ -56,6 +56,9 @@ let isPseudo = 0; let isCodeGenOnly = 0; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; + // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; @@ -212,7 +215,6 @@ let Outs = (outs); let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0); let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0); - let InsDPP = (ins Src0RC32:$vdst, Src0RC32:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); let InsSDWA = (ins Src0RC32:$vdst, Int32InputMods:$src0_modifiers, VCSrc_b32:$src0, @@ -426,6 +428,8 @@ let Uses = ps.Uses; let SchedRW = ps.SchedRW; let hasSideEffects = ps.hasSideEffects; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; let AsmMatchConverter = "cvtSdwaVOP1"; bits<8> vdst; @@ -441,6 +445,8 @@ let Uses = ps.Uses; let SchedRW = ps.SchedRW; let hasSideEffects = ps.hasSideEffects; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; bits<8> vdst; let Inst{8-0} = 0xfa; // dpp Index: lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP2Instructions.td +++ lib/Target/AMDGPU/VOP2Instructions.td @@ -72,6 +72,9 @@ let isPseudo = 0; let isCodeGenOnly = 0; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; + // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; @@ -157,13 +160,13 @@ let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); let Ins64 = getIns64, 3, HasModifiers, Src0Mod, Src1Mod, Src2Mod>.ret; - let InsDPP = (ins FP32InputMods:$src0_modifiers, Src0RC32:$src0, - FP32InputMods:$src1_modifiers, Src1RC32:$src1, + let InsDPP = (ins FP32InputMods:$src0_modifiers, Src0DPP:$src0, + FP32InputMods:$src1_modifiers, Src1DPP:$src1, VGPR_32:$src2, // stub argument dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); - let InsSDWA = (ins FP32InputMods:$src0_modifiers, Src0RC32:$src0, - FP32InputMods:$src1_modifiers, Src1RC32:$src1, + let InsSDWA = (ins FP32InputMods:$src0_modifiers, Src0SDWA:$src0, + FP32InputMods:$src1_modifiers, Src1SDWA:$src1, VGPR_32:$src2, // stub argument clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, src0_sel:$src0_sel, src1_sel:$src1_sel); @@ -557,6 +560,8 @@ let Uses = ps.Uses; let SchedRW = ps.SchedRW; let hasSideEffects = ps.hasSideEffects; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; let AsmMatchConverter = "cvtSdwaVOP2"; bits<8> vdst; @@ -574,6 +579,8 @@ let Uses = ps.Uses; let SchedRW = ps.SchedRW; let hasSideEffects = ps.hasSideEffects; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; bits<8> vdst; bits<8> src1; Index: lib/Target/AMDGPU/VOPCInstructions.td =================================================================== --- lib/Target/AMDGPU/VOPCInstructions.td +++ lib/Target/AMDGPU/VOPCInstructions.td @@ -71,6 +71,9 @@ let isPseudo = 0; let isCodeGenOnly = 0; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; + // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; @@ -826,6 +829,8 @@ let AsmMatchConverter = "cvtSdwaVOPC"; let isCompare = ps.isCompare; let isCommutable = ps.isCommutable; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; bits<8> src1; let Inst{8-0} = 0xf9; // sdwa Index: lib/Target/AMDGPU/VOPInstructions.td =================================================================== --- lib/Target/AMDGPU/VOPInstructions.td +++ lib/Target/AMDGPU/VOPInstructions.td @@ -118,6 +118,9 @@ let isPseudo = 0; let isCodeGenOnly = 0; + let Constraints = ps.Constraints; + let DisableEncoding = ps.DisableEncoding; + // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; Index: test/MC/Disassembler/AMDGPU/dpp_vi.txt =================================================================== --- test/MC/Disassembler/AMDGPU/dpp_vi.txt +++ test/MC/Disassembler/AMDGPU/dpp_vi.txt @@ -85,5 +85,10 @@ 0xfa 0x00 0x00 0x02 0x00 0x01 0x99 0xa1 # VI: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1] +0xfa 0x00 0x00 0x02 0x00 0x01 0x69 0xa1 -0xfa 0x00 0x00 0x02 0x00 0x01 0x69 0xa1 \ No newline at end of file +# VI: v_mac_f32_dpp v76, v76, v114 quad_perm:[2,3,0,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xe4,0x98,0x2c,0x4c,0x4e,0x00,0xff] +0xfa 0xe4 0x98 0x2c 0x4c 0x4e 0x00 0xff + +# VI: v_mac_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1] +0xfa 0x06 0x02 0x46 0x02 0x01 0x09 0xa1 \ No newline at end of file Index: test/MC/Disassembler/AMDGPU/sdwa_vi.txt =================================================================== --- test/MC/Disassembler/AMDGPU/sdwa_vi.txt +++ test/MC/Disassembler/AMDGPU/sdwa_vi.txt @@ -300,8 +300,11 @@ # VI: v_mul_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x44,0x02,0x06,0x05,0x02] 0xf9 0x06 0x02 0x44 0x02 0x06 0x05 0x02 -# VI: v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46] -0x02,0x07,0x02,0x46 +# VI: v_mac_f32_sdwa v15, v99, v194 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:WORD_0 src1_sel:DWORD ; encoding: [0xf9,0x84,0x1f,0x2c,0x63,0x0e,0x04,0x06] +0xf9 0x84 0x1f 0x2c 0x63 0x0e 0x04 0x06 + +# VI: v_mac_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x46,0x02,0x06,0x05,0x02] +0xf9 0x06 0x02 0x46 0x02 0x06 0x05 0x02 # VI: v_add_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x4c,0x02,0x06,0x05,0x02] 0xf9 0x06 0x02 0x4c 0x02 0x06 0x05 0x02