Index: include/llvm/CodeGen/BasicTTIImpl.h =================================================================== --- include/llvm/CodeGen/BasicTTIImpl.h +++ include/llvm/CodeGen/BasicTTIImpl.h @@ -462,9 +462,9 @@ // cost of the split itself. Count that as 1, to be consistent with // TLI->getTypeLegalizationCost(). if ((TLI->getTypeAction(Src->getContext(), TLI->getValueType(DL, Src)) == - TargetLowering::TypeSplitVector) || + TargetLowering::SplitVector) || (TLI->getTypeAction(Dst->getContext(), TLI->getValueType(DL, Dst)) == - TargetLowering::TypeSplitVector)) { + TargetLowering::SplitVector)) { Type *SplitDst = VectorType::get(Dst->getVectorElementType(), Dst->getVectorNumElements() / 2); Type *SplitSrc = VectorType::get(Src->getVectorElementType(), Index: include/llvm/Target/TargetLowering.h =================================================================== --- include/llvm/Target/TargetLowering.h +++ include/llvm/Target/TargetLowering.h @@ -104,28 +104,19 @@ Legal, // The target natively supports this operation. Promote, // This operation should be executed in a larger type. Expand, // Try to expand this to other ops, otherwise use a libcall. + + SoftenFloat, // Convert this float to a same size integer type, + ScalarizeVector, // Replace this one-element vector with its element. + SplitVector, // Split this vector into two of half the size. + WidenVector, // This vector should be widened into a larger vector. + LibCall, // Don't try to expand this to other ops, always use a libcall. Custom // Use the LowerOperation hook to implement custom lowering. }; - /// This enum indicates whether a types are legal for a target, and if not, - /// what action should be used to make them valid. - enum LegalizeTypeAction : uint8_t { - TypeLegal, // The target natively supports this type. - TypePromoteInteger, // Replace this integer with a larger one. - TypeExpandInteger, // Split this integer into two of half the size. - TypeSoftenFloat, // Convert this float to a same size integer type, - // if an operation is not supported in target HW. - TypeExpandFloat, // Split this float into two of half the size. - TypeScalarizeVector, // Replace this one-element vector with its element. - TypeSplitVector, // Split this vector into two of half the size. - TypeWidenVector, // This vector should be widened into a larger vector. - TypePromoteFloat // Replace this float with a larger one. - }; - /// LegalizeKind holds the legalization kind that needs to happen to EVT /// in order to type-legalize it. - typedef std::pair LegalizeKind; + typedef std::pair LegalizeKind; /// Enum that describes how the target represents true/false values. enum BooleanContent { @@ -226,13 +217,13 @@ bool hasExtractBitsInsn() const { return HasExtractBitsInsn; } /// Return the preferred vector type legalization action. - virtual TargetLoweringBase::LegalizeTypeAction + virtual TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT) const { // The default action for one element vectors is to scalarize if (VT.getVectorNumElements() == 1) - return TypeScalarizeVector; + return ScalarizeVector; // The default action for other vectors is to promote - return TypePromoteInteger; + return Promote; } // There are two general methods for expanding a BUILD_VECTOR node: @@ -538,21 +529,21 @@ } class ValueTypeActionImpl { - /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum + /// ValueTypeActions - For each value type, keep a LegalizeAction enum /// that indicates how instruction selection should deal with the type. - LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE]; + LegalizeAction ValueTypeActions[MVT::LAST_VALUETYPE]; public: ValueTypeActionImpl() { std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), - TypeLegal); + Legal); } - LegalizeTypeAction getTypeAction(MVT VT) const { + LegalizeAction getTypeAction(MVT VT) const { return ValueTypeActions[VT.SimpleTy]; } - void setTypeAction(MVT VT, LegalizeTypeAction Action) { + void setTypeAction(MVT VT, LegalizeAction Action) { ValueTypeActions[VT.SimpleTy] = Action; } }; @@ -565,10 +556,10 @@ /// legal (return 'Legal') or we need to promote it to a larger type (return /// 'Promote'), or we need to expand it into multiple registers of smaller /// integer type (return 'Expand'). 'Custom' is not an option. - LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { + LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { return getTypeConversion(Context, VT).first; } - LegalizeTypeAction getTypeAction(MVT VT) const { + LegalizeAction getTypeAction(MVT VT) const { return ValueTypeActions.getTypeAction(VT); } @@ -590,9 +581,9 @@ assert(!VT.isVector()); while (true) { switch (getTypeAction(Context, VT)) { - case TypeLegal: + case Legal: return VT; - case TypeExpandInteger: + case Expand: VT = getTypeToTransformTo(Context, VT); break; default: @@ -1379,9 +1370,8 @@ return false; // Only do the transform if the value won't be split into multiple // registers. - LegalizeTypeAction Action = getTypeAction(Context, VT); - return Action != TypeExpandInteger && Action != TypeExpandFloat && - Action != TypeSplitVector; + LegalizeAction Action = getTypeAction(Context, VT); + return Action != Expand && Action != SplitVector; } //===--------------------------------------------------------------------===// Index: lib/CodeGen/CodeGenPrepare.cpp =================================================================== --- lib/CodeGen/CodeGenPrepare.cpp +++ lib/CodeGen/CodeGenPrepare.cpp @@ -956,11 +956,9 @@ // If these values will be promoted, find out what they will be promoted // to. This helps us consider truncates on PPC as noop copies when they // are. - if (TLI.getTypeAction(CI->getContext(), SrcVT) == - TargetLowering::TypePromoteInteger) + if (TLI.getTypeAction(CI->getContext(), SrcVT) == TargetLowering::Promote) SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); - if (TLI.getTypeAction(CI->getContext(), DstVT) == - TargetLowering::TypePromoteInteger) + if (TLI.getTypeAction(CI->getContext(), DstVT) == TargetLowering::Promote) DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); // If, after promotion, these are the same types, this is a noop copy. @@ -5514,7 +5512,7 @@ if (TLI && TLI->getTypeAction(CI->getContext(), TLI->getValueType(*DL, CI->getType())) == - TargetLowering::TypeExpandInteger) { + TargetLowering::Expand) { return SinkCast(CI); } else { bool MadeChange = moveExtToFormExtLoad(I); Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5891,7 +5891,7 @@ // Check if any splitting is required. if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) != - TargetLowering::TypeSplitVector) + TargetLowering::SplitVector) return SDValue(); SDValue MaskLo, MaskHi, Lo, Hi; std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG); @@ -5952,7 +5952,7 @@ // Check if any splitting is required. if (TLI.getTypeAction(*DAG.getContext(), VT) != - TargetLowering::TypeSplitVector) + TargetLowering::SplitVector) return SDValue(); SDValue MaskLo, MaskHi, Lo, Hi; @@ -6026,7 +6026,7 @@ // Check if any splitting is required. if (TLI.getTypeAction(*DAG.getContext(), VT) != - TargetLowering::TypeSplitVector) + TargetLowering::SplitVector) return SDValue(); SDValue MaskLo, MaskHi, Lo, Hi; @@ -6101,7 +6101,7 @@ // Check if any splitting is required. if (TLI.getTypeAction(*DAG.getContext(), VT) != - TargetLowering::TypeSplitVector) + TargetLowering::SplitVector) return SDValue(); SDValue MaskLo, MaskHi, Lo, Hi; @@ -6220,7 +6220,7 @@ // Check if any splitting is required. if (TLI.getTypeAction(*DAG.getContext(), VT) != - TargetLowering::TypeSplitVector) + TargetLowering::SplitVector) return SDValue(); SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH; @@ -12119,7 +12119,7 @@ LastLegalType = i+1; // Or check whether a truncstore is legal. } else if (TLI.getTypeAction(Context, StoreTy) == - TargetLowering::TypePromoteInteger) { + TargetLowering::Promote) { EVT LegalizedStoredValueTy = TLI.getTypeToTransformTo(Context, StoredVal.getValueType()); if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) && @@ -12291,7 +12291,7 @@ LastLegalIntegerType = i + 1; // Or check whether a truncstore and extload is legal. else if (TLI.getTypeAction(Context, StoreTy) == - TargetLowering::TypePromoteInteger) { + TargetLowering::Promote) { EVT LegalizedStoredValueTy = TLI.getTypeToTransformTo(Context, StoreTy); if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) && Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -909,13 +909,13 @@ #ifndef NDEBUG for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == - TargetLowering::TypeLegal || + TargetLowering::Legal || TLI.isTypeLegal(Node->getValueType(i))) && "Unexpected illegal type!"); for (const SDValue &Op : Node->op_values()) assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == - TargetLowering::TypeLegal || + TargetLowering::Legal || TLI.isTypeLegal(Op.getValueType()) || Op.getOpcode() == ISD::TargetConstant) && "Unexpected illegal type!"); @@ -1136,6 +1136,8 @@ case TargetLowering::Promote: PromoteNode(Node); return; + default: + llvm_unreachable("unexpected legalize action"); } } Index: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -458,11 +458,11 @@ // hard-float FP_EXTEND rather than FP16_TO_FP. if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) { Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); - if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat) + if (getTypeAction(MVT::f32) == TargetLowering::SoftenFloat) AddToWorklist(Op.getNode()); } - if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) { + if (getTypeAction(Op.getValueType()) == TargetLowering::Promote) { Op = GetPromotedFloat(Op); // If the promotion did the FP_EXTEND to the destination type for us, // there's nothing left to do here. @@ -1961,18 +1961,18 @@ switch (getTypeAction(VecVT)) { default: break; - case TargetLowering::TypeScalarizeVector: { + case TargetLowering::ScalarizeVector: { SDValue Res = GetScalarizedVector(N->getOperand(0)); ReplaceValueWith(SDValue(N, 0), Res); return SDValue(); } - case TargetLowering::TypeWidenVector: { + case TargetLowering::WidenVector: { Vec = GetWidenedVector(Vec); SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx); ReplaceValueWith(SDValue(N, 0), Res); return SDValue(); } - case TargetLowering::TypeSplitVector: { + case TargetLowering::SplitVector: { SDValue Lo, Hi; GetSplitVector(Vec, Lo, Hi); Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -249,32 +249,31 @@ SDLoc dl(N); switch (getTypeAction(InVT)) { - case TargetLowering::TypeLegal: + case TargetLowering::Legal: break; - case TargetLowering::TypePromoteInteger: - if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) - // The input promotes to the same size. Convert the promoted value. - return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); + case TargetLowering::Promote: + if (InVT.isInteger()) { + if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) + // The input promotes to the same size. Convert the promoted value. + return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); + } else { + // Convert the promoted float by hand. + SDValue PromotedOp = GetPromotedFloat(InOp); + return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); + } break; - case TargetLowering::TypeSoftenFloat: + case TargetLowering::SoftenFloat: // Promote the integer operand by hand. return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); - case TargetLowering::TypePromoteFloat: { - // Convert the promoted float by hand. - SDValue PromotedOp = GetPromotedFloat(InOp); - return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); - break; - } - case TargetLowering::TypeExpandInteger: - case TargetLowering::TypeExpandFloat: + case TargetLowering::Expand: break; - case TargetLowering::TypeScalarizeVector: + case TargetLowering::ScalarizeVector: // Convert the element to an integer and promote it by hand. if (!NOutVT.isVector()) return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, BitConvertToInteger(GetScalarizedVector(InOp))); break; - case TargetLowering::TypeSplitVector: { + case TargetLowering::SplitVector: { // For example, i32 = BITCAST v2i16 on alpha. Convert the split // pieces of the input into integers and reassemble in the final type. SDValue Lo, Hi; @@ -291,12 +290,15 @@ JoinIntegers(Lo, Hi)); return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); } - case TargetLowering::TypeWidenVector: + case TargetLowering::WidenVector: // The input is widened to the same size. Convert to the widened value. // Make sure that the outgoing value is not a vector, because this would // make us bitcast between two vectors which are legalized in different ways. if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); + break; + default: + llvm_unreachable("unexpected legalize action"); } return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, @@ -435,7 +437,7 @@ SDLoc dl(N); if (getTypeAction(N->getOperand(0).getValueType()) - == TargetLowering::TypePromoteInteger) { + == TargetLowering::Promote) { SDValue Res = GetPromotedInteger(N->getOperand(0)); assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); @@ -594,10 +596,10 @@ SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); if (LHS.getValueType() != RHS.getValueType()) { - if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger && + if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote && !LHS.getValueType().isVector()) LHS = GetPromotedInteger(LHS); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger && + if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote && !RHS.getValueType().isVector()) RHS = GetPromotedInteger(RHS); } @@ -614,9 +616,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); - if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger) + if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote) LHS = GetPromotedInteger(LHS); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) + if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote) RHS = ZExtPromotedInteger(RHS); return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS); } @@ -657,9 +659,9 @@ SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); // The input value must be properly sign extended. - if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger) + if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote) LHS = SExtPromotedInteger(LHS); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) + if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote) RHS = ZExtPromotedInteger(RHS); return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); } @@ -668,9 +670,9 @@ SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); // The input value must be properly zero extended. - if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger) + if (getTypeAction(LHS.getValueType()) == TargetLowering::Promote) LHS = ZExtPromotedInteger(LHS); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) + if (getTypeAction(RHS.getValueType()) == TargetLowering::Promote) RHS = ZExtPromotedInteger(RHS); return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); } @@ -683,14 +685,14 @@ switch (getTypeAction(InOp.getValueType())) { default: llvm_unreachable("Unknown type action!"); - case TargetLowering::TypeLegal: - case TargetLowering::TypeExpandInteger: + case TargetLowering::Legal: + case TargetLowering::Expand: Res = InOp; break; - case TargetLowering::TypePromoteInteger: + case TargetLowering::Promote: Res = GetPromotedInteger(InOp); break; - case TargetLowering::TypeSplitVector: + case TargetLowering::SplitVector: EVT InVT = InOp.getValueType(); assert(InVT.isVector() && "Cannot split scalar types"); unsigned NumElts = InVT.getVectorNumElements(); @@ -1168,14 +1170,14 @@ if (TLI.isTypeLegal(DataVT)) Mask = PromoteTargetBoolean(Mask, DataVT); else { - if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) + if (getTypeAction(DataVT) == TargetLowering::Promote) return PromoteIntOp_MSTORE(N, 3); - else if (getTypeAction(DataVT) == TargetLowering::TypeWidenVector) + else if (getTypeAction(DataVT) == TargetLowering::WidenVector) return WidenVecOp_MSTORE(N, 3); else { - assert (getTypeAction(DataVT) == TargetLowering::TypeSplitVector); + assert (getTypeAction(DataVT) == TargetLowering::SplitVector); return SplitVecOp_MSTORE(N, 3); } } @@ -1855,7 +1857,7 @@ // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. assert(getTypeAction(Op.getValueType()) == - TargetLowering::TypePromoteInteger && + TargetLowering::Promote && "Only know how to promote this result!"); SDValue Res = GetPromotedInteger(Op); assert(Res.getValueType() == N->getValueType(0) && @@ -2007,7 +2009,8 @@ EVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); - if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) + if (Op.getValueType().isFloatingPoint() && + getTypeAction(Op.getValueType()) == TargetLowering::Promote) Op = GetPromotedFloat(Op); RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); @@ -2022,7 +2025,8 @@ EVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); - if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) + if (Op.getValueType().isFloatingPoint() && + getTypeAction(Op.getValueType()) == TargetLowering::Promote) Op = GetPromotedFloat(Op); RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); @@ -2430,7 +2434,7 @@ // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. assert(getTypeAction(Op.getValueType()) == - TargetLowering::TypePromoteInteger && + TargetLowering::Promote && "Only know how to promote this result!"); SDValue Res = GetPromotedInteger(Op); assert(Res.getValueType() == N->getValueType(0) && @@ -2682,7 +2686,7 @@ // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. assert(getTypeAction(Op.getValueType()) == - TargetLowering::TypePromoteInteger && + TargetLowering::Promote && "Only know how to promote this result!"); SDValue Res = GetPromotedInteger(Op); assert(Res.getValueType() == N->getValueType(0) && @@ -3332,7 +3336,7 @@ // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to // type.. if (getTypeAction(N->getOperand(0).getValueType()) - == TargetLowering::TypePromoteInteger) { + == TargetLowering::Promote) { SDValue Promoted; switch(N->getOpcode()) { Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -60,13 +60,13 @@ TargetLowering::ValueTypeActionImpl ValueTypeActions; /// Return how we should legalize values of this type. - TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { + TargetLowering::LegalizeAction getTypeAction(EVT VT) const { return TLI.getTypeAction(*DAG.getContext(), VT); } /// Return true if this type is legal on this target. bool isTypeLegal(EVT VT) const { - return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal; + return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::Legal; } /// Return true if this is a simple legal type. Index: lib/CodeGen/SelectionDAG/LegalizeTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -225,22 +225,32 @@ for (unsigned i = 0, NumResults = N->getNumValues(); i < NumResults; ++i) { EVT ResultVT = N->getValueType(i); switch (getTypeAction(ResultVT)) { - case TargetLowering::TypeLegal: + case TargetLowering::Legal: break; // The following calls must take care of *all* of the node's results, // not just the illegal result they were passed (this includes results // with a legal type). Results can be remapped using ReplaceValueWith, // or their promoted/expanded/etc values registered in PromotedIntegers, // ExpandedIntegers etc. - case TargetLowering::TypePromoteInteger: - PromoteIntegerResult(N, i); + case TargetLowering::Promote: + if (ResultVT.isInteger()) { + PromoteIntegerResult(N, i); + } else { + assert(ResultVT.isFloatingPoint() && "expected float type"); + PromoteFloatResult(N, i); + } Changed = true; goto NodeDone; - case TargetLowering::TypeExpandInteger: - ExpandIntegerResult(N, i); + case TargetLowering::Expand: + if (ResultVT.isInteger()) { + ExpandIntegerResult(N, i); + } else { + assert(ResultVT.isFloatingPoint() && "expected float type"); + ExpandFloatResult(N, i); + } Changed = true; goto NodeDone; - case TargetLowering::TypeSoftenFloat: + case TargetLowering::SoftenFloat: Changed = SoftenFloatResult(N, i); if (Changed) goto NodeDone; @@ -248,26 +258,20 @@ assert(isLegalInHWReg(ResultVT) && "Unchanged SoftenFloatResult should be legal in register!"); goto ScanOperands; - case TargetLowering::TypeExpandFloat: - ExpandFloatResult(N, i); - Changed = true; - goto NodeDone; - case TargetLowering::TypeScalarizeVector: + case TargetLowering::ScalarizeVector: ScalarizeVectorResult(N, i); Changed = true; goto NodeDone; - case TargetLowering::TypeSplitVector: + case TargetLowering::SplitVector: SplitVectorResult(N, i); Changed = true; goto NodeDone; - case TargetLowering::TypeWidenVector: + case TargetLowering::WidenVector: WidenVectorResult(N, i); Changed = true; goto NodeDone; - case TargetLowering::TypePromoteFloat: - PromoteFloatResult(N, i); - Changed = true; - goto NodeDone; + default: + llvm_unreachable("unexpected legalize action"); } } @@ -284,43 +288,47 @@ EVT OpVT = N->getOperand(i).getValueType(); switch (getTypeAction(OpVT)) { - case TargetLowering::TypeLegal: + case TargetLowering::Legal: continue; // The following calls must either replace all of the node's results // using ReplaceValueWith, and return "false"; or update the node's // operands in place, and return "true". - case TargetLowering::TypePromoteInteger: - NeedsReanalyzing = PromoteIntegerOperand(N, i); + case TargetLowering::Promote: + if (OpVT.isInteger()) { + NeedsReanalyzing = PromoteIntegerOperand(N, i); + } else { + assert(OpVT.isFloatingPoint() && "expected float type"); + NeedsReanalyzing = PromoteFloatOperand(N, i); + } Changed = true; break; - case TargetLowering::TypeExpandInteger: - NeedsReanalyzing = ExpandIntegerOperand(N, i); + case TargetLowering::Expand: + if (OpVT.isInteger()) { + NeedsReanalyzing = ExpandIntegerOperand(N, i); + } else { + assert(OpVT.isFloatingPoint() && "expected float type"); + NeedsReanalyzing = ExpandFloatOperand(N, i); + } Changed = true; break; - case TargetLowering::TypeSoftenFloat: + case TargetLowering::SoftenFloat: NeedsReanalyzing = SoftenFloatOperand(N, i); Changed = true; break; - case TargetLowering::TypeExpandFloat: - NeedsReanalyzing = ExpandFloatOperand(N, i); - Changed = true; - break; - case TargetLowering::TypeScalarizeVector: + case TargetLowering::ScalarizeVector: NeedsReanalyzing = ScalarizeVectorOperand(N, i); Changed = true; break; - case TargetLowering::TypeSplitVector: + case TargetLowering::SplitVector: NeedsReanalyzing = SplitVectorOperand(N, i); Changed = true; break; - case TargetLowering::TypeWidenVector: + case TargetLowering::WidenVector: NeedsReanalyzing = WidenVectorOperand(N, i); Changed = true; break; - case TargetLowering::TypePromoteFloat: - NeedsReanalyzing = PromoteFloatOperand(N, i); - Changed = true; - break; + default: + llvm_unreachable("unexpected legalize action"); } break; } Index: lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp +++ lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp @@ -47,13 +47,17 @@ // Handle some special cases efficiently. switch (getTypeAction(InVT)) { - case TargetLowering::TypeLegal: - case TargetLowering::TypePromoteInteger: + case TargetLowering::Legal: break; - case TargetLowering::TypePromoteFloat: + case TargetLowering::Promote: + if (InVT.isInteger()) { + break; + } + + assert(InVT.isFloatingPoint() && "unexpected value type"); llvm_unreachable("Bitcast of a promotion-needing float should never need" "expansion"); - case TargetLowering::TypeSoftenFloat: { + case TargetLowering::SoftenFloat: { // Expand the floating point operand only if it was converted to integers. // Otherwise, it is a legal type like f128 that can be saved in a register. auto SoftenedOp = GetSoftenedFloat(InOp); @@ -64,8 +68,7 @@ Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; } - case TargetLowering::TypeExpandInteger: - case TargetLowering::TypeExpandFloat: { + case TargetLowering::Expand: { auto &DL = DAG.getDataLayout(); // Convert the expanded pieces of the input. GetExpandedOp(InOp, Lo, Hi); @@ -76,20 +79,20 @@ Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; } - case TargetLowering::TypeSplitVector: + case TargetLowering::SplitVector: GetSplitVector(InOp, Lo, Hi); if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) std::swap(Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; - case TargetLowering::TypeScalarizeVector: + case TargetLowering::ScalarizeVector: // Convert the element instead. SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; - case TargetLowering::TypeWidenVector: { + case TargetLowering::WidenVector: { assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); InOp = GetWidenedVector(InOp); EVT LoVT, HiVT; @@ -101,6 +104,8 @@ Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; } + default: + llvm_unreachable("unexpected legalize action"); } if (InVT.isVector() && OutVT.isInteger()) { @@ -524,7 +529,7 @@ if (Cond.getValueType().isVector()) { // Check if there are already splitted versions of the vector available and // use those instead of splitting the mask operand again. - if (getTypeAction(Cond.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Cond.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Cond, CL, CH); else std::tie(CL, CH) = DAG.SplitVector(Cond, dl); Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -239,7 +239,7 @@ // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is // legal and was not scalarized. // See the similar logic in ScalarizeVecRes_VSETCC - if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { + if (getTypeAction(OpVT) == TargetLowering::ScalarizeVector) { Op = GetScalarizedVector(Op); } else { EVT VT = OpVT.getVectorElementType(); @@ -372,7 +372,7 @@ SDLoc DL(N); // The result needs scalarizing, but it's not a given that the source does. - if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { + if (getTypeAction(OpVT) == TargetLowering::ScalarizeVector) { LHS = GetScalarizedVector(LHS); RHS = GetScalarizedVector(RHS); } else { @@ -732,15 +732,13 @@ // Handle some special cases efficiently. switch (getTypeAction(InVT)) { - case TargetLowering::TypeLegal: - case TargetLowering::TypePromoteInteger: - case TargetLowering::TypePromoteFloat: - case TargetLowering::TypeSoftenFloat: - case TargetLowering::TypeScalarizeVector: - case TargetLowering::TypeWidenVector: + case TargetLowering::Legal: + case TargetLowering::Promote: + case TargetLowering::SoftenFloat: + case TargetLowering::ScalarizeVector: + case TargetLowering::WidenVector: break; - case TargetLowering::TypeExpandInteger: - case TargetLowering::TypeExpandFloat: + case TargetLowering::Expand: // A scalar to vector conversion, where the scalar needs expansion. // If the vector is being split in two then we can just convert the // expanded pieces. @@ -753,13 +751,15 @@ return; } break; - case TargetLowering::TypeSplitVector: + case TargetLowering::SplitVector: // If the input is a vector that needs to be split, convert each split // piece of the input now. GetSplitVector(InOp, Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); return; + default: + llvm_unreachable("unexpected legalize action"); } // In the general case, convert the input to an integer and split it by hand. @@ -897,7 +897,7 @@ SDValue RHSLo, RHSHi; SDValue RHS = N->getOperand(1); EVT RHSVT = RHS.getValueType(); - if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector) + if (getTypeAction(RHSVT) == TargetLowering::SplitVector) GetSplitVector(RHS, RHSLo, RHSHi); else std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS)); @@ -1081,7 +1081,7 @@ // Split Mask operand SDValue MaskLo, MaskHi; - if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Mask, MaskLo, MaskHi); else std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl); @@ -1091,7 +1091,7 @@ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT); SDValue Src0Lo, Src0Hi; - if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Src0.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Src0, Src0Lo, Src0Hi); else std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl); @@ -1142,7 +1142,7 @@ // Split Mask operand SDValue MaskLo, MaskHi; - if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Mask, MaskLo, MaskHi); else std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl); @@ -1153,13 +1153,13 @@ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT); SDValue Src0Lo, Src0Hi; - if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Src0.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Src0, Src0Lo, Src0Hi); else std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl); SDValue IndexHi, IndexLo; - if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Index.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Index, IndexLo, IndexHi); else std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl); @@ -1216,7 +1216,7 @@ // If the input also splits, handle it directly for a compile time speedup. // Otherwise split it by hand. EVT InVT = N->getOperand(0).getValueType(); - if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) + if (getTypeAction(InVT) == TargetLowering::SplitVector) GetSplitVector(N->getOperand(0), Lo, Hi); else std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0); @@ -1646,7 +1646,7 @@ unsigned Alignment = MGT->getOriginalAlignment(); SDValue MaskLo, MaskHi; - if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector) // Split Mask operand GetSplitVector(Mask, MaskLo, MaskHi); else @@ -1657,13 +1657,13 @@ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT); SDValue Src0Lo, Src0Hi; - if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Src0.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Src0, Src0Lo, Src0Hi); else std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl); SDValue IndexHi, IndexLo; - if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Index.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Index, IndexLo, IndexHi); else std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl); @@ -1716,14 +1716,14 @@ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT); SDValue DataLo, DataHi; - if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Data.getValueType()) == TargetLowering::SplitVector) // Split Data operand GetSplitVector(Data, DataLo, DataHi); else std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL); SDValue MaskLo, MaskHi; - if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector) // Split Mask operand GetSplitVector(Mask, MaskLo, MaskHi); else @@ -1779,21 +1779,21 @@ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT); SDValue DataLo, DataHi; - if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Data.getValueType()) == TargetLowering::SplitVector) // Split Data operand GetSplitVector(Data, DataLo, DataHi); else std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL); SDValue MaskLo, MaskHi; - if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Mask.getValueType()) == TargetLowering::SplitVector) // Split Mask operand GetSplitVector(Mask, MaskLo, MaskHi); else std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL); SDValue IndexHi, IndexLo; - if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector) + if (getTypeAction(Index.getValueType()) == TargetLowering::SplitVector) GetSplitVector(Index, IndexLo, IndexHi); else std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL); @@ -2317,7 +2317,7 @@ unsigned Opcode = N->getOpcode(); unsigned InVTNumElts = InVT.getVectorNumElements(); const SDNodeFlags *Flags = N->getFlags(); - if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { + if (getTypeAction(InVT) == TargetLowering::WidenVector) { InOp = GetWidenedVector(N->getOperand(0)); InVT = InOp.getValueType(); InVTNumElts = InVT.getVectorNumElements(); @@ -2403,7 +2403,7 @@ EVT InSVT = InVT.getVectorElementType(); unsigned InVTNumElts = InVT.getVectorNumElements(); - if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { + if (getTypeAction(InVT) == TargetLowering::WidenVector) { InOp = GetWidenedVector(InOp); InVT = InOp.getValueType(); if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) { @@ -2469,7 +2469,7 @@ SDValue ShOp = N->getOperand(1); EVT ShVT = ShOp.getValueType(); - if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { + if (getTypeAction(ShVT) == TargetLowering::WidenVector) { ShOp = GetWidenedVector(ShOp); ShVT = ShOp.getValueType(); } @@ -2513,30 +2513,33 @@ SDLoc dl(N); switch (getTypeAction(InVT)) { - case TargetLowering::TypeLegal: + case TargetLowering::Legal: break; - case TargetLowering::TypePromoteInteger: - // If the incoming type is a vector that is being promoted, then - // we know that the elements are arranged differently and that we - // must perform the conversion using a stack slot. - if (InVT.isVector()) - break; + case TargetLowering::Promote: + if (InVT.isInteger()) { + // If the incoming type is a vector that is being promoted, then + // we know that the elements are arranged differently and that we + // must perform the conversion using a stack slot. + if (InVT.isVector()) + break; - // If the InOp is promoted to the same size, convert it. Otherwise, - // fall out of the switch and widen the promoted input. - InOp = GetPromotedInteger(InOp); - InVT = InOp.getValueType(); - if (WidenVT.bitsEq(InVT)) - return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); - break; - case TargetLowering::TypeSoftenFloat: - case TargetLowering::TypePromoteFloat: - case TargetLowering::TypeExpandInteger: - case TargetLowering::TypeExpandFloat: - case TargetLowering::TypeScalarizeVector: - case TargetLowering::TypeSplitVector: + // If the InOp is promoted to the same size, convert it. Otherwise, + // fall out of the switch and widen the promoted input. + InOp = GetPromotedInteger(InOp); + InVT = InOp.getValueType(); + if (WidenVT.bitsEq(InVT)) + return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); + break; + } else { + assert(InVT.isFloatingPoint() && "expected float value type"); + break; + } + case TargetLowering::Expand: + case TargetLowering::SoftenFloat: + case TargetLowering::ScalarizeVector: + case TargetLowering::SplitVector: break; - case TargetLowering::TypeWidenVector: + case TargetLowering::WidenVector: // If the InOp is widened to the same size, convert it. Otherwise, fall // out of the switch and widen the widened input. InOp = GetWidenedVector(InOp); @@ -2545,6 +2548,8 @@ // The input widens to the same size. Convert to the widen value. return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); break; + default: + llvm_unreachable("unexpected value type"); } unsigned WidenSize = WidenVT.getSizeInBits(); @@ -2617,7 +2622,7 @@ unsigned NumOperands = N->getNumOperands(); bool InputWidened = false; // Indicates we need to widen the input. - if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { + if (getTypeAction(InVT) != TargetLowering::WidenVector) { if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { // Add undef vectors to widen to correct length. unsigned NumConcat = WidenVT.getVectorNumElements() / @@ -2686,7 +2691,7 @@ SDValue Idx = N->getOperand(1); SDLoc dl(N); - if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) + if (getTypeAction(InOp.getValueType()) == TargetLowering::WidenVector) InOp = GetWidenedVector(InOp); EVT InVT = InOp.getValueType(); @@ -2762,7 +2767,7 @@ ISD::LoadExtType ExtType = N->getExtensionType(); SDLoc dl(N); - if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector) + if (getTypeAction(MaskVT) == TargetLowering::WidenVector) Mask = GetWidenedVector(Mask); else { EVT BoolVT = getSetCCResultType(WidenVT); @@ -2836,7 +2841,7 @@ EVT CondEltVT = CondVT.getVectorElementType(); EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), CondEltVT, WidenNumElts); - if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) + if (getTypeAction(CondVT) == TargetLowering::WidenVector) Cond1 = GetWidenedVector(Cond1); // If we have to split the condition there is no point in widening the @@ -2844,7 +2849,7 @@ // widening the condition operand -> splitting the condition operand -> // splitting the select -> widening the select. Instead split this select // further and widen the resulting type. - if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) { + if (getTypeAction(CondVT) == TargetLowering::SplitVector) { SDValue SplitSelect = SplitVecOp_VSELECT(N, 0); SDValue Res = ModifyToType(SplitSelect, WidenVT); return Res; @@ -2928,7 +2933,7 @@ // The input and output types often differ here, and it could be that while // we'd prefer to widen the result type, the input operands have been split. // In this case, we also need to split the result of this node as well. - if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) { + if (getTypeAction(InVT) == TargetLowering::SplitVector) { SDValue SplitVSetCC = SplitVecOp_VSETCC(N); SDValue Res = ModifyToType(SplitVSetCC, WidenVT); return Res; @@ -3020,7 +3025,7 @@ // If some legalization strategy other than widening is used on the operand, // we can't safely assume that just extending the low lanes is the correct // transformation. - if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector) + if (getTypeAction(InOp.getValueType()) != TargetLowering::WidenVector) return WidenVecOp_Convert(N); InOp = GetWidenedVector(InOp); assert(VT.getVectorNumElements() < @@ -3091,7 +3096,7 @@ SDLoc dl(N); unsigned NumElts = VT.getVectorNumElements(); SDValue InOp = N->getOperand(0); - if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) + if (getTypeAction(InOp.getValueType()) == TargetLowering::WidenVector) InOp = GetWidenedVector(InOp); EVT InVT = InOp.getValueType(); EVT InEltVT = InVT.getVectorElementType(); @@ -3149,7 +3154,7 @@ unsigned NumOperands = N->getNumOperands(); for (unsigned i=0; i < NumOperands; ++i) { SDValue InOp = N->getOperand(i); - if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) + if (getTypeAction(InOp.getValueType()) == TargetLowering::WidenVector) InOp = GetWidenedVector(InOp); for (unsigned j=0; j < NumInElts; ++j) Ops[Idx++] = DAG.getNode( @@ -3197,7 +3202,7 @@ SDValue WideVal = GetWidenedVector(StVal); SDLoc dl(N); - if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector) + if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::WidenVector) Mask = GetWidenedVector(Mask); else { // The mask should be widened as well. @@ -3313,8 +3318,8 @@ if (MemVT.getSizeInBits() <= WidenEltWidth) break; auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT); - if ((Action == TargetLowering::TypeLegal || - Action == TargetLowering::TypePromoteInteger) && + if ((Action == TargetLowering::Legal || + (MemVT.isInteger() && Action == TargetLowering::Promote)) && (WidenWidth % MemVTWidth) == 0 && isPowerOf2_32(WidenWidth / MemVTWidth) && (MemVTWidth <= Width || Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1101,8 +1101,8 @@ // needs to be promoted, for example v8i8 on ARM. In this case, promote the // inserted value (the type does not need to match the vector element type). // Any extra bits introduced will be truncated away. - if (VT.isVector() && TLI->getTypeAction(*getContext(), EltVT) == - TargetLowering::TypePromoteInteger) { + if (VT.isVector() && VT.isInteger() && + TLI->getTypeAction(*getContext(), EltVT) == TargetLowering::Promote) { EltVT = TLI->getTypeToTransformTo(*getContext(), EltVT); APInt NewVal = Elt->getValue().zextOrTrunc(EltVT.getSizeInBits()); Elt = ConstantInt::get(*getContext(), NewVal); @@ -1113,9 +1113,8 @@ // Then bitcast to the type requested. // Legalizing constants too early makes the DAGCombiner's job harder so we // only legalize if the DAG tells us we must produce legal types. - else if (NewNodesMustHaveLegalTypes && VT.isVector() && - TLI->getTypeAction(*getContext(), EltVT) == - TargetLowering::TypeExpandInteger) { + else if (NewNodesMustHaveLegalTypes && VT.isVector() && VT.isInteger() && + TLI->getTypeAction(*getContext(), EltVT) == TargetLowering::Expand) { const APInt &NewVal = Elt->getValue(); EVT ViaEltVT = TLI->getTypeToTransformTo(*getContext(), EltVT); unsigned ViaEltSizeInBits = ViaEltVT.getSizeInBits(); Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2758,7 +2758,7 @@ // We care about the legality of the operation after it has been type // legalized. - while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal && + while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::Legal && VT != TLI.getTypeToTransformTo(Ctx, VT)) VT = TLI.getTypeToTransformTo(Ctx, VT); Index: lib/CodeGen/TargetLoweringBase.cpp =================================================================== --- lib/CodeGen/TargetLoweringBase.cpp +++ lib/CodeGen/TargetLoweringBase.cpp @@ -1009,17 +1009,17 @@ MVT SVT = VT.getSimpleVT(); assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); MVT NVT = TransformToType[SVT.SimpleTy]; - LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); + LegalizeAction LA = ValueTypeActions.getTypeAction(SVT); - assert((LA == TypeLegal || LA == TypeSoftenFloat || - ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && + assert((LA == Legal || LA == SoftenFloat || + ValueTypeActions.getTypeAction(NVT) != Promote) && "Promote may not follow Expand or Promote"); - if (LA == TypeSplitVector) + if (LA == SplitVector) return LegalizeKind(LA, EVT::getVectorVT(Context, SVT.getVectorElementType(), SVT.getVectorNumElements() / 2)); - if (LA == TypeScalarizeVector) + if (LA == ScalarizeVector) return LegalizeKind(LA, SVT.getVectorElementType()); return LegalizeKind(LA, NVT); } @@ -1034,13 +1034,13 @@ assert(NVT != VT && "Unable to round integer VT"); LegalizeKind NextStep = getTypeConversion(Context, NVT); // Avoid multi-step promotion. - if (NextStep.first == TypePromoteInteger) + if (NextStep.first == Promote) return NextStep; // Return rounded integer type. - return LegalizeKind(TypePromoteInteger, NVT); + return LegalizeKind(Promote, NVT); } - return LegalizeKind(TypeExpandInteger, + return LegalizeKind(Expand, EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); } @@ -1050,7 +1050,7 @@ // Vectors with only one element are always scalarized. if (NumElts == 1) - return LegalizeKind(TypeScalarizeVector, EltVT); + return LegalizeKind(ScalarizeVector, EltVT); // Try to widen vector elements until the element type is a power of two and // promote it to a legal type later on, for example: @@ -1061,7 +1061,7 @@ if (!VT.isPow2VectorType()) { NumElts = (unsigned)NextPowerOf2(NumElts); EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); - return LegalizeKind(TypeWidenVector, NVT); + return LegalizeKind(WidenVector, NVT); } // Examine the element type. @@ -1069,8 +1069,8 @@ // If type is to be expanded, split the vector. // <4 x i140> -> <2 x i140> - if (LK.first == TypeExpandInteger) - return LegalizeKind(TypeSplitVector, + if (LK.first == Expand) + return LegalizeKind(SplitVector, EVT::getVectorVT(Context, EltVT, NumElts / 2)); // Promote the integer element types until a legal vector type is found @@ -1094,8 +1094,8 @@ // Build a new vector type and check if it is legal. MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); // Found a legal promoted vector type. - if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) - return LegalizeKind(TypePromoteInteger, + if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == Legal) + return LegalizeKind(Promote, EVT::getVectorVT(Context, EltVT, NumElts)); } @@ -1120,19 +1120,19 @@ break; // If this type is legal then widen the vector. - if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) - return LegalizeKind(TypeWidenVector, LargerVector); + if (ValueTypeActions.getTypeAction(LargerVector) == Legal) + return LegalizeKind(WidenVector, LargerVector); } // Widen odd vectors to next power of two. if (!VT.isPow2VectorType()) { EVT NVT = VT.getPow2VectorType(Context); - return LegalizeKind(TypeWidenVector, NVT); + return LegalizeKind(WidenVector, NVT); } // Vectors with illegal element types are expanded. EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); - return LegalizeKind(TypeSplitVector, NVT); + return LegalizeKind(SplitVector, NVT); } static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, @@ -1335,8 +1335,7 @@ NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); - ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, - TypeExpandInteger); + ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, Expand); } // Inspect all of the ValueType's smaller than the largest integer @@ -1350,7 +1349,7 @@ } else { RegisterTypeForVT[IntReg] = TransformToType[IntReg] = (const MVT::SimpleValueType)LegalIntReg; - ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); + ValueTypeActions.setTypeAction(IVT, Promote); } } @@ -1360,12 +1359,12 @@ NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; RegisterTypeForVT[MVT::ppcf128] = MVT::f64; TransformToType[MVT::ppcf128] = MVT::f64; - ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); + ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); } else { NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; TransformToType[MVT::ppcf128] = MVT::i128; - ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); + ValueTypeActions.setTypeAction(MVT::ppcf128, SoftenFloat); } } @@ -1375,7 +1374,7 @@ NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; TransformToType[MVT::f128] = MVT::i128; - ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); + ValueTypeActions.setTypeAction(MVT::f128, SoftenFloat); } // Decide how to handle f64. If the target does not have native f64 support, @@ -1384,7 +1383,7 @@ NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; TransformToType[MVT::f64] = MVT::i64; - ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); + ValueTypeActions.setTypeAction(MVT::f64, SoftenFloat); } // Decide how to handle f32. If the target does not have native f32 support, @@ -1393,7 +1392,7 @@ NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; TransformToType[MVT::f32] = MVT::i32; - ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); + ValueTypeActions.setTypeAction(MVT::f32, SoftenFloat); } // Decide how to handle f16. If the target does not have native f16 support, @@ -1403,7 +1402,7 @@ NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; TransformToType[MVT::f16] = MVT::f32; - ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); + ValueTypeActions.setTypeAction(MVT::f16, Promote); } // Loop over all of the vector value types to see which need transformations. @@ -1416,9 +1415,9 @@ MVT EltVT = VT.getVectorElementType(); unsigned NElts = VT.getVectorNumElements(); bool IsLegalWiderType = false; - LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); + LegalizeAction PreferredAction = getPreferredVectorAction(VT); switch (PreferredAction) { - case TypePromoteInteger: { + case Promote: { // Try to promote the elements of integer vectors. If no legal // promotion was found, fall through to the widen-vector method. for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { @@ -1430,7 +1429,7 @@ TransformToType[i] = SVT; RegisterTypeForVT[i] = SVT; NumRegistersForVT[i] = 1; - ValueTypeActions.setTypeAction(VT, TypePromoteInteger); + ValueTypeActions.setTypeAction(VT, Promote); IsLegalWiderType = true; break; } @@ -1438,7 +1437,7 @@ if (IsLegalWiderType) break; } - case TypeWidenVector: { + case WidenVector: { // Try to widen the vector. for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { MVT SVT = (MVT::SimpleValueType) nVT; @@ -1447,7 +1446,7 @@ TransformToType[i] = SVT; RegisterTypeForVT[i] = SVT; NumRegistersForVT[i] = 1; - ValueTypeActions.setTypeAction(VT, TypeWidenVector); + ValueTypeActions.setTypeAction(VT, WidenVector); IsLegalWiderType = true; break; } @@ -1455,8 +1454,8 @@ if (IsLegalWiderType) break; } - case TypeSplitVector: - case TypeScalarizeVector: { + case SplitVector: + case ScalarizeVector: { MVT IntermediateVT; MVT RegisterVT; unsigned NumIntermediates; @@ -1468,17 +1467,17 @@ if (NVT == VT) { // Type is already a power of 2. The default action is to split. TransformToType[i] = MVT::Other; - if (PreferredAction == TypeScalarizeVector) - ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); - else if (PreferredAction == TypeSplitVector) - ValueTypeActions.setTypeAction(VT, TypeSplitVector); + if (PreferredAction == ScalarizeVector) + ValueTypeActions.setTypeAction(VT, ScalarizeVector); + else if (PreferredAction == SplitVector) + ValueTypeActions.setTypeAction(VT, SplitVector); else // Set type action according to the number of elements. - ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector - : TypeSplitVector); + ValueTypeActions.setTypeAction(VT, NElts == 1 ? ScalarizeVector + : SplitVector); } else { TransformToType[i] = NVT; - ValueTypeActions.setTypeAction(VT, TypeWidenVector); + ValueTypeActions.setTypeAction(VT, WidenVector); } break; } @@ -1531,8 +1530,8 @@ // are wider, then we should convert to that legal vector type. // This handles things like <2 x float> -> <4 x float> and // <4 x i1> -> <4 x i32>. - LegalizeTypeAction TA = getTypeAction(Context, VT); - if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { + LegalizeAction TA = getTypeAction(Context, VT); + if (NumElts != 1 && (TA == WidenVector || TA == Promote)) { EVT RegisterEVT = getTypeToTransformTo(Context, VT); if (isTypeLegal(RegisterEVT)) { IntermediateVT = RegisterEVT; @@ -1762,10 +1761,10 @@ while (true) { LegalizeKind LK = getTypeConversion(C, MTy); - if (LK.first == TypeLegal) + if (LK.first == Legal) return std::make_pair(Cost, MTy.getSimpleVT()); - if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) + if (LK.first == SplitVector || LK.first == Expand) Cost *= 2; // Do not loop with f128 type. Index: lib/Target/AArch64/AArch64ISelLowering.h =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.h +++ lib/Target/AArch64/AArch64ISelLowering.h @@ -375,7 +375,7 @@ bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; bool useLoadStackGuardNode() const override; - TargetLoweringBase::LegalizeTypeAction + TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT) const override; /// If the target has a standard location for the stack protector cookie, Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5070,9 +5070,9 @@ // AArch64 Advanced SIMD Support //===----------------------------------------------------------------------===// -/// WidenVector - Given a value in the V64 register class, produce the +/// Given a value in the V64 register class, produce the /// equivalent value in the V128 register class. -static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) { +static SDValue CreateWidenedVector(SDValue V64Reg, SelectionDAG &DAG) { EVT VT = V64Reg.getValueType(); unsigned NarrowSize = VT.getVectorNumElements(); MVT EltTy = VT.getVectorElementType().getSimpleVT(); @@ -5648,7 +5648,7 @@ llvm_unreachable("Invalid vector element type?"); if (VT.getSizeInBits() == 64) - OpLHS = WidenVector(OpLHS, DAG); + OpLHS = CreateWidenedVector(OpLHS, DAG); SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64); return DAG.getNode(Opcode, dl, VT, OpLHS, Lane); } @@ -5791,16 +5791,16 @@ // SelectionDAGBuilder may have "helpfully" already extracted or conatenated // to make a vector of the same size as this SHUFFLE. We can ignore the - // extract entirely, and canonicalise the concat using WidenVector. + // extract entirely, and canonicalise the concat using CreateWidenedVector. if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { Lane += cast(V1.getOperand(1))->getZExtValue(); V1 = V1.getOperand(0); } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2; Lane -= Idx * VT.getVectorNumElements() / 2; - V1 = WidenVector(V1.getOperand(Idx), DAG); + V1 = CreateWidenedVector(V1.getOperand(Idx), DAG); } else if (VT.getSizeInBits() == 64) - V1 = WidenVector(V1, DAG); + V1 = CreateWidenedVector(V1, DAG); return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64)); } @@ -6529,7 +6529,7 @@ SDValue Lane = Value.getOperand(1); Value = Value.getOperand(0); if (Value.getValueSizeInBits() == 64) - Value = WidenVector(Value, DAG); + Value = CreateWidenedVector(Value, DAG); unsigned Opcode = getDUPLANEOp(VT.getVectorElementType()); return DAG.getNode(Opcode, dl, VT, Value, Lane); @@ -6646,7 +6646,7 @@ // For V64 types, we perform insertion by expanding the value // to a V128 type and perform the insertion on that. SDLoc DL(Op); - SDValue WideVec = WidenVector(Op.getOperand(0), DAG); + SDValue WideVec = CreateWidenedVector(Op.getOperand(0), DAG); EVT WideTy = WideVec.getValueType(); SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, @@ -6680,7 +6680,7 @@ // For V64 types, we perform extraction by expanding the value // to a V128 type and perform the extraction on that. SDLoc DL(Op); - SDValue WideVec = WidenVector(Op.getOperand(0), DAG); + SDValue WideVec = CreateWidenedVector(Op.getOperand(0), DAG); EVT WideTy = WideVec.getValueType(); EVT ExtrTy = WideTy.getVectorElementType(); @@ -8319,7 +8319,7 @@ // canonicalise to that. if (N0 == N1 && VT.getVectorNumElements() == 2) { assert(VT.getScalarSizeInBits() == 64); - return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG), + return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, CreateWidenedVector(N0, DAG), DAG.getConstant(0, dl, MVT::i64)); } @@ -10481,14 +10481,14 @@ return 3; } -TargetLoweringBase::LegalizeTypeAction +TargetLoweringBase::LegalizeAction AArch64TargetLowering::getPreferredVectorAction(EVT VT) const { MVT SVT = VT.getSimpleVT(); // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8, // v4i16, v2i32 instead of to promote. if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 || SVT == MVT::v1f32) - return TypeWidenVector; + return WidenVector; return TargetLoweringBase::getPreferredVectorAction(VT); } Index: lib/Target/AMDGPU/SIISelLowering.h =================================================================== --- lib/Target/AMDGPU/SIISelLowering.h +++ lib/Target/AMDGPU/SIISelLowering.h @@ -141,7 +141,7 @@ bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; - TargetLoweringBase::LegalizeTypeAction + TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT) const override; bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Index: lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIISelLowering.cpp +++ lib/Target/AMDGPU/SIISelLowering.cpp @@ -695,10 +695,10 @@ return AMDGPU::isUniformMMO(MemNode->getMemOperand()); } -TargetLoweringBase::LegalizeTypeAction +TargetLoweringBase::LegalizeAction SITargetLowering::getPreferredVectorAction(EVT VT) const { if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16)) - return TypeSplitVector; + return SplitVector; return TargetLoweringBase::getPreferredVectorAction(VT); } Index: lib/Target/NVPTX/NVPTXISelLowering.h =================================================================== --- lib/Target/NVPTX/NVPTXISelLowering.h +++ lib/Target/NVPTX/NVPTXISelLowering.h @@ -507,7 +507,7 @@ return MVT::i32; } - TargetLoweringBase::LegalizeTypeAction + TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT) const override; // Get the degree of precision we want from 32-bit floating point division Index: lib/Target/NVPTX/NVPTXISelLowering.cpp =================================================================== --- lib/Target/NVPTX/NVPTXISelLowering.cpp +++ lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1035,10 +1035,10 @@ return nullptr; } -TargetLoweringBase::LegalizeTypeAction +TargetLoweringBase::LegalizeAction NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const { if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1) - return TypeSplitVector; + return SplitVector; return TargetLoweringBase::getPreferredVectorAction(VT); } Index: lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- lib/Target/PowerPC/PPCISelLowering.h +++ lib/Target/PowerPC/PPCISelLowering.h @@ -502,10 +502,10 @@ /// of v4i8's and shuffle them. This will turn into a mess of 8 extending /// loads, moves back into VSR's (or memory ops if we don't have moves) and /// then the VPERM for the shuffle. All in all a very slow sequence. - TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) + TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT) const override { if (VT.getScalarSizeInBits() % 8 == 0) - return TypeWidenVector; + return WidenVector; return TargetLoweringBase::getPreferredVectorAction(VT); } Index: lib/Target/SystemZ/SystemZISelLowering.h =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.h +++ lib/Target/SystemZ/SystemZISelLowering.h @@ -365,7 +365,7 @@ // want to clobber the upper 32 bits of a GPR unnecessarily. return MVT::i32; } - TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) + TargetLoweringBase::LegalizeAction getPreferredVectorAction(EVT VT) const override { // Widen subvectors to the full width rather than promoting integer // elements. This is better because: @@ -379,7 +379,7 @@ // (c) there are no multiplication instructions for the widest integer // type (v2i64). if (VT.getScalarSizeInBits() % 8 == 0) - return TypeWidenVector; + return WidenVector; return TargetLoweringBase::getPreferredVectorAction(VT); } EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, Index: lib/Target/X86/X86ISelLowering.h =================================================================== --- lib/Target/X86/X86ISelLowering.h +++ lib/Target/X86/X86ISelLowering.h @@ -1036,7 +1036,7 @@ bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; /// \brief Customize the preferred legalization strategy for certain types. - LegalizeTypeAction getPreferredVectorAction(EVT VT) const override; + LegalizeAction getPreferredVectorAction(EVT VT) const override; bool isIntDivCheap(EVT VT, AttributeSet Attr) const override; Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -590,7 +590,7 @@ if (UseX87) { if (Subtarget.is64Bit() && Subtarget.hasMMX()) { addRegisterClass(MVT::f128, &X86::FR128RegClass); - ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); + ValueTypeActions.setTypeAction(MVT::f128, SoftenFloat); setOperationAction(ISD::FABS , MVT::f128, Custom); setOperationAction(ISD::FNEG , MVT::f128, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom); @@ -1730,12 +1730,12 @@ return Subtarget.isTargetMachO() && Subtarget.is64Bit(); } -TargetLoweringBase::LegalizeTypeAction +TargetLoweringBase::LegalizeAction X86TargetLowering::getPreferredVectorAction(EVT VT) const { if (ExperimentalVectorWideningLegalization && VT.getVectorNumElements() != 1 && VT.getVectorElementType().getSimpleVT() != MVT::i1) - return TypeWidenVector; + return WidenVector; return TargetLoweringBase::getPreferredVectorAction(VT); } @@ -1769,7 +1769,8 @@ if (Subtarget.hasBWI() && Subtarget.hasVLX()) return MVT::getVectorVT(MVT::i1, NumElts); - if (!isTypeLegal(VT) && getTypeAction(Context, VT) == TypePromoteInteger) { + if (!isTypeLegal(VT) && VT.isInteger() && + getTypeAction(Context, VT) == Promote) { EVT LegalVT = getTypeToTransformTo(Context, VT); EltVT = LegalVT.getVectorElementType().getSimpleVT(); }