Index: include/llvm/CodeGen/GlobalISel/RegisterBank.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/RegisterBank.h
+++ include/llvm/CodeGen/GlobalISel/RegisterBank.h
@@ -41,11 +41,8 @@
   friend RegisterBankInfo;
 
 public:
-  /// The default constructor will leave the object in
-  /// an invalid state. I.e. isValid() == false.
-  /// The fields must be updated to fix that and only
-  /// RegisterBankInfo instances are allowed to do that
-  RegisterBank();
+  RegisterBank(unsigned ID, const char *Name, unsigned Size,
+               const uint32_t *ContainedRegClasses);
 
   /// Get the identifier of this register bank.
   unsigned getID() const { return ID; }
Index: include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -396,9 +396,6 @@
     llvm_unreachable("This constructor should not be executed");
   }
 
-  void setRegBankData(unsigned ID, const char *Name, unsigned Size,
-                      const uint32_t *CoveredClasses);
-
   /// Get the register bank identified by \p ID.
   RegisterBank &getRegBank(unsigned ID) {
     assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
Index: lib/CodeGen/GlobalISel/RegisterBank.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBank.cpp
+++ lib/CodeGen/GlobalISel/RegisterBank.cpp
@@ -19,7 +19,12 @@
 
 const unsigned RegisterBank::InvalidID = UINT_MAX;
 
-RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {}
+RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
+                           const uint32_t *CoveredClasses)
+    : ID(ID), Name(Name), Size(Size) {
+  ContainedRegClasses.resize(200);
+  ContainedRegClasses.setBitsInMask(CoveredClasses);
+}
 
 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
   assert(isValid() && "Invalid register bank");
Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -56,8 +56,10 @@
                                    unsigned NumRegBanks)
     : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
 #ifndef NDEBUG
-  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx)
+  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
     assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
+    assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
+  }
 #endif // NDEBUG
 }
 
@@ -81,17 +83,6 @@
   return true;
 }
 
-void RegisterBankInfo::setRegBankData(unsigned ID, const char *Name,
-                                      unsigned Size,
-                                      const uint32_t *CoveredClasses) {
-  RegisterBank &RB = getRegBank(ID);
-  RB.ID = ID;
-  RB.Name = Name;
-  RB.Size = Size;
-  RB.ContainedRegClasses.resize(200);
-  RB.ContainedRegClasses.setBitsInMask(CoveredClasses);
-}
-
 const RegisterBank *
 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
                              const TargetRegisterInfo &TRI) const {
Index: lib/Target/AArch64/AArch64GenRegisterBankInfo.def
===================================================================
--- lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+++ lib/Target/AArch64/AArch64GenRegisterBankInfo.def
@@ -141,9 +141,9 @@
     0,
 };
 
-RegisterBank GPRRegBank;
-RegisterBank FPRRegBank;
-RegisterBank CCRRegBank;
+RegisterBank GPRRegBank(AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData);
+RegisterBank FPRRegBank(AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData);
+RegisterBank CCRRegBank(AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData);
 
 RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
 
Index: lib/Target/AArch64/AArch64RegisterBankInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -41,25 +41,30 @@
   if (AlreadyInit)
     return;
   AlreadyInit = true;
-  // The GPR register bank is fully defined by all the registers in
-  // GR64all + its subclasses.
-  setRegBankData(AArch64::GPRRegBankID, "GPR", 64, AArch64::GPRCoverageData);
+
   const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
   (void)RBGPR;
   assert(&AArch64::GPRRegBank == &RBGPR &&
          "The order in RegBanks is messed up");
+
+  const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
+  (void)RBFPR;
+  assert(&AArch64::FPRRegBank == &RBFPR &&
+         "The order in RegBanks is messed up");
+
+  const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
+  (void)RBCCR;
+  assert(&AArch64::CCRRegBank == &RBCCR &&
+         "The order in RegBanks is messed up");
+
+  // The GPR register bank is fully defined by all the registers in
+  // GR64all + its subclasses.
   assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
          "Subclass not added?");
   assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
 
   // The FPR register bank is fully defined by all the registers in
   // GR64all + its subclasses.
-  setRegBankData(AArch64::FPRRegBankID, "FPR", 512, AArch64::FPRCoverageData);
-
-  const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
-  (void)RBFPR;
-  assert(&AArch64::FPRRegBank == &RBFPR &&
-         "The order in RegBanks is messed up");
   assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
          "Subclass not added?");
   assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
@@ -67,12 +72,6 @@
   assert(RBFPR.getSize() == 512 &&
          "FPRs should hold up to 512-bit via QQQQ sequence");
 
-  // Initialize the CCR bank.
-  setRegBankData(AArch64::CCRRegBankID, "CCR", 32, AArch64::CCRCoverageData);
-  const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
-  (void)RBCCR;
-  assert(&AArch64::CCRRegBank == &RBCCR &&
-         "The order in RegBanks is messed up");
   assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
          "Class not added?");
   assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
Index: lib/Target/ARM/ARMRegisterBankInfo.cpp
===================================================================
--- lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -55,7 +55,7 @@
     0,
 };
 
-RegisterBank GPRRegBank;
+RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
 RegisterBank *RegBanks[] = {&GPRRegBank};
 
 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
@@ -77,11 +77,11 @@
     return;
   AlreadyInit = true;
 
-  // Initialize the GPR bank.
-  setRegBankData(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
   const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
   (void)RBGPR;
   assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
+
+  // Initialize the GPR bank.
   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
          "Subclass not added?");
   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&