Index: include/llvm/CodeGen/GlobalISel/RegisterBank.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/RegisterBank.h
+++ include/llvm/CodeGen/GlobalISel/RegisterBank.h
@@ -47,11 +47,14 @@
   friend RegisterBankInfo;
 
 public:
-  /// The default constructor will leave the object in
-  /// an invalid state. I.e. isValid() == false.
-  /// The fields must be updated to fix that and only
-  /// RegisterBankInfo instances are allowed to do that
-  RegisterBank();
+  RegisterBank(const DataTy &Data);
+
+  /// Finish initialization of the register bank. This is only needed because
+  /// TRI isn't available for the static initializer.
+  ///
+  /// FIXME: Eliminate the need for this by having tablegen hard-code the
+  ///        register class count.
+  void finishInit(const TargetRegisterInfo &TRI);
 
   /// Get the identifier of this register bank.
   unsigned getID() const { return Data.ID; }
Index: include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -396,9 +396,6 @@
     llvm_unreachable("This constructor should not be executed");
   }
 
-  void setRegBankData(unsigned ID, const RegisterBank::DataTy &Data,
-                      const TargetRegisterInfo &TRI);
-
   /// Get the register bank identified by \p ID.
   RegisterBank &getRegBank(unsigned ID) {
     assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
Index: lib/CodeGen/GlobalISel/RegisterBank.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBank.cpp
+++ lib/CodeGen/GlobalISel/RegisterBank.cpp
@@ -19,7 +19,16 @@
 
 const RegisterBank::DataTy InvalidData = {UINT_MAX, nullptr, 0, 0};
 
-RegisterBank::RegisterBank() : Data(InvalidData) {}
+RegisterBank::RegisterBank(const RegisterBank::DataTy &Data) : Data(Data) {}
+
+void RegisterBank::finishInit(const TargetRegisterInfo &TRI) {
+  // Populate ContainedRegClasses from the static data. We can't do this in the
+  // constructor because we don't have TRI in a static initializer.
+  uint32_t Mask[] = {(uint32_t)Data.CoveredClasses,
+                     (uint32_t)(Data.CoveredClasses >> 32)};
+  ContainedRegClasses.resize(TRI.getNumRegClasses());
+  ContainedRegClasses.setBitsInMask(Mask);
+}
 
 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
   assert(isValid() && "Invalid register bank");
Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -80,18 +80,6 @@
   return true;
 }
 
-void RegisterBankInfo::setRegBankData(unsigned ID,
-                                      const RegisterBank::DataTy &Data,
-                                      const TargetRegisterInfo &TRI) {
-  RegisterBank &RB = getRegBank(ID);
-  RB.Data = Data;
-
-  uint32_t Mask[] = {(uint32_t)Data.CoveredClasses,
-                     (uint32_t)(Data.CoveredClasses >> 32)};
-  RB.ContainedRegClasses.resize(TRI.getNumRegClasses());
-  RB.ContainedRegClasses.setBitsInMask(Mask);
-}
-
 const RegisterBank *
 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
                              const TargetRegisterInfo &TRI) const {
Index: lib/Target/AArch64/AArch64GenRegisterBankInfo.def
===================================================================
--- lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+++ lib/Target/AArch64/AArch64GenRegisterBankInfo.def
@@ -73,9 +73,9 @@
     {AArch64::CCRRegBankID, "CCR", 32, 1ull << AArch64::CCRRegClassID},
 };
 
-RegisterBank GPRRegBank;
-RegisterBank FPRRegBank;
-RegisterBank CCRRegBank;
+RegisterBank GPRRegBank(RegisterBankData[GPRRegBankID]);
+RegisterBank FPRRegBank(RegisterBankData[FPRRegBankID]);
+RegisterBank CCRRegBank(RegisterBankData[CCRRegBankID]);
 
 RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
 
Index: lib/Target/AArch64/AArch64RegisterBankInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -41,26 +41,34 @@
   if (AlreadyInit)
     return;
   AlreadyInit = true;
-  // The GPR register bank is fully defined by all the registers in
-  // GR64all + its subclasses.
-  setRegBankData(AArch64::GPRRegBankID,
-                 AArch64::RegisterBankData[AArch64::GPRRegBankID], TRI);
+
   const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
   (void)RBGPR;
   assert(&AArch64::GPRRegBank == &RBGPR &&
          "The order in RegBanks is messed up");
+
+  const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
+  (void)RBFPR;
+  assert(&AArch64::FPRRegBank == &RBFPR &&
+         "The order in RegBanks is messed up");
+
+  const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
+  (void)RBCCR;
+  assert(&AArch64::CCRRegBank == &RBCCR &&
+         "The order in RegBanks is messed up");
+
+  // Finish the initialization of the register banks.
+  for (auto &ID : {AArch64::GPRRegBankID, AArch64::FPRRegBankID, AArch64::CCRRegBankID})
+    getRegBank(ID).finishInit(TRI);
+
+  // The GPR register bank is fully defined by all the registers in
+  // GR64all + its subclasses.
   assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
          "Subclass not added?");
   assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
 
   // The FPR register bank is fully defined by all the registers in
   // GR64all + its subclasses.
-  setRegBankData(AArch64::FPRRegBankID,
-                 AArch64::RegisterBankData[AArch64::FPRRegBankID], TRI);
-  const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
-  (void)RBFPR;
-  assert(&AArch64::FPRRegBank == &RBFPR &&
-         "The order in RegBanks is messed up");
   assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
          "Subclass not added?");
   assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
@@ -68,12 +76,6 @@
   assert(RBFPR.getSize() == 512 &&
          "FPRs should hold up to 512-bit via QQQQ sequence");
 
-  setRegBankData(AArch64::CCRRegBankID,
-                 AArch64::RegisterBankData[AArch64::CCRRegBankID], TRI);
-  const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
-  (void)RBCCR;
-  assert(&AArch64::CCRRegBank == &RBCCR &&
-         "The order in RegBanks is messed up");
   assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
          "Class not added?");
   assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");