Index: include/llvm/CodeGen/GlobalISel/RegisterBank.h =================================================================== --- include/llvm/CodeGen/GlobalISel/RegisterBank.h +++ include/llvm/CodeGen/GlobalISel/RegisterBank.h @@ -29,12 +29,13 @@ class RegisterBank { public: typedef struct { + unsigned ID; + const char *Name; unsigned Size; + uint64_t CoveredClasses; } DataTy; private: - unsigned ID; - const char *Name; DataTy Data; BitVector ContainedRegClasses; @@ -53,11 +54,11 @@ RegisterBank(); /// Get the identifier of this register bank. - unsigned getID() const { return ID; } + unsigned getID() const { return Data.ID; } /// Get a user friendly name of this register bank. /// Should be used only for debugging purposes. - const char *getName() const { return Name; } + const char *getName() const { return Data.Name; } /// Get the maximal size in bits that fits in this register bank. unsigned getSize() const { return Data.Size; } Index: include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h =================================================================== --- include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -384,10 +384,6 @@ /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks /// RegisterBank instances. - /// - /// \note For the verify method to succeed all the \p NumRegBanks - /// must be initialized by createRegisterBank and updated with - /// addRegBankCoverage RegisterBank. RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks); /// This constructor is meaningless. @@ -400,15 +396,8 @@ llvm_unreachable("This constructor should not be executed"); } - /// Create a new register bank with the given parameter and add it - /// to RegBanks. - /// \pre \p ID must not already be used. - /// \pre \p ID < NumRegBanks. - void createRegisterBank(unsigned ID, const char *Name); - - void setRegBankData(unsigned ID, const RegisterBank::DataTy &Data); - void setRegBankCoverage(unsigned ID, uint64_t CoveredClasses, - const TargetRegisterInfo &TRI); + void setRegBankData(unsigned ID, const RegisterBank::DataTy &Data, + const TargetRegisterInfo &TRI); /// Get the register bank identified by \p ID. RegisterBank &getRegBank(unsigned ID) { Index: lib/CodeGen/GlobalISel/RegisterBank.cpp =================================================================== --- lib/CodeGen/GlobalISel/RegisterBank.cpp +++ lib/CodeGen/GlobalISel/RegisterBank.cpp @@ -17,9 +17,9 @@ using namespace llvm; -const unsigned RegisterBank::InvalidID = UINT_MAX; +const RegisterBank::DataTy InvalidData = {UINT_MAX, nullptr, 0, 0}; -RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Data() {} +RegisterBank::RegisterBank() : Data(InvalidData) {} bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { assert(isValid() && "Invalid register bank"); @@ -58,7 +58,7 @@ } bool RegisterBank::isValid() const { - return ID != InvalidID && Name != nullptr && getSize() != 0 && + return getID() != InvalidData.ID && getName() != nullptr && getSize() != 0 && // A register bank that does not cover anything is useless. !ContainedRegClasses.empty(); } Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp =================================================================== --- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -80,26 +80,14 @@ return true; } -void RegisterBankInfo::createRegisterBank(unsigned ID, const char *Name) { - DEBUG(dbgs() << "Create register bank: " << ID << " with name \"" << Name - << "\"\n"); - RegisterBank &RegBank = getRegBank(ID); - assert(RegBank.getID() == RegisterBank::InvalidID && - "A register bank should be created only once"); - RegBank.ID = ID; - RegBank.Name = Name; -} - -void RegisterBankInfo::setRegBankData(unsigned ID, const RegisterBank::DataTy &Data) { +void RegisterBankInfo::setRegBankData(unsigned ID, + const RegisterBank::DataTy &Data, + const TargetRegisterInfo &TRI) { RegisterBank &RB = getRegBank(ID); RB.Data = Data; -} -void RegisterBankInfo::setRegBankCoverage(unsigned ID, uint64_t CoveredClasses, - const TargetRegisterInfo &TRI) { - uint32_t Mask[] = {(uint32_t)CoveredClasses, - (uint32_t)(CoveredClasses >> 32)}; - RegisterBank &RB = getRegBank(ID); + uint32_t Mask[] = {(uint32_t)Data.CoveredClasses, + (uint32_t)(Data.CoveredClasses >> 32)}; RB.ContainedRegClasses.resize(TRI.getNumRegClasses()); RB.ContainedRegClasses.setBitsInMask(Mask); } Index: lib/Target/AArch64/AArch64GenRegisterBankInfo.def =================================================================== --- lib/Target/AArch64/AArch64GenRegisterBankInfo.def +++ lib/Target/AArch64/AArch64GenRegisterBankInfo.def @@ -18,6 +18,61 @@ namespace llvm { namespace AArch64 { +const RegisterBank::DataTy RegisterBankData[] = { + {AArch64::GPRRegBankID, "GPR", 64, + (1ull << AArch64::GPR32allRegClassID) | + (1ull << AArch64::GPR32RegClassID) | + (1ull << AArch64::GPR32spRegClassID) | + (1ull << AArch64::GPR32commonRegClassID) | + (1ull << AArch64::GPR32sponlyRegClassID) | + (1ull << AArch64::GPR64allRegClassID) | + (1ull << AArch64::GPR64RegClassID) | + (1ull << AArch64::GPR64spRegClassID) | + (1ull << AArch64::GPR64commonRegClassID) | + (1ull << AArch64::tcGPR64RegClassID) | + (1ull << AArch64::GPR64sponlyRegClassID)}, + {AArch64::FPRRegBankID, "FPR", 512, + (1ull << AArch64::FPR8RegClassID) | (1ull << AArch64::FPR16RegClassID) | + (1ull << AArch64::FPR32RegClassID) | + (1ull << AArch64::FPR64RegClassID) | (1ull << AArch64::DDRegClassID) | + (1ull << AArch64::FPR128RegClassID) | + (1ull << AArch64::FPR128_loRegClassID) | + (1ull << AArch64::DDDRegClassID) | (1ull << AArch64::DDDDRegClassID) | + (1ull << AArch64::QQRegClassID) | + (1ull << AArch64::QQ_with_qsub0_in_FPR128_loRegClassID) | + (1ull << AArch64::QQ_with_qsub1_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQRegClassID) | + (1ull << AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQQRegClassID) | + (1ull << AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID) | + (1ull << AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID) | + (1ull << AArch64:: + QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID)}, + {AArch64::CCRRegBankID, "CCR", 32, 1ull << AArch64::CCRRegClassID}, +}; + RegisterBank GPRRegBank; RegisterBank FPRRegBank; RegisterBank CCRRegBank; Index: lib/Target/AArch64/AArch64RegisterBankInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -30,10 +30,6 @@ #error "You shouldn't build this" #endif -const RegisterBank::DataTy GPRData = {64}; -const RegisterBank::DataTy FPRData = {512}; -const RegisterBank::DataTy CCRData = {32}; - AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) : RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) { static bool AlreadyInit = false; @@ -45,24 +41,10 @@ if (AlreadyInit) return; AlreadyInit = true; - // Initialize the GPR bank. - createRegisterBank(AArch64::GPRRegBankID, "GPR"); // The GPR register bank is fully defined by all the registers in // GR64all + its subclasses. - setRegBankData(AArch64::GPRRegBankID, GPRData); - setRegBankCoverage(AArch64::GPRRegBankID, - (1ull << AArch64::GPR32allRegClassID) | - (1ull << AArch64::GPR32RegClassID) | - (1ull << AArch64::GPR32spRegClassID) | - (1ull << AArch64::GPR32commonRegClassID) | - (1ull << AArch64::GPR32sponlyRegClassID) | - (1ull << AArch64::GPR64allRegClassID) | - (1ull << AArch64::GPR64RegClassID) | - (1ull << AArch64::GPR64spRegClassID) | - (1ull << AArch64::GPR64commonRegClassID) | - (1ull << AArch64::tcGPR64RegClassID) | - (1ull << AArch64::GPR64sponlyRegClassID), - TRI); + setRegBankData(AArch64::GPRRegBankID, + AArch64::RegisterBankData[AArch64::GPRRegBankID], TRI); const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); (void)RBGPR; assert(&AArch64::GPRRegBank == &RBGPR && @@ -71,50 +53,10 @@ "Subclass not added?"); assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); - // Initialize the FPR bank. - createRegisterBank(AArch64::FPRRegBankID, "FPR"); // The FPR register bank is fully defined by all the registers in // GR64all + its subclasses. - setRegBankData(AArch64::FPRRegBankID, FPRData); - setRegBankCoverage( - AArch64::FPRRegBankID, - (1ull << AArch64::FPR8RegClassID) | (1ull << AArch64::FPR16RegClassID) | - (1ull << AArch64::FPR32RegClassID) | (1ull << AArch64::FPR64RegClassID) | - (1ull << AArch64::DDRegClassID) | (1ull << AArch64::FPR128RegClassID) | - (1ull << AArch64::FPR128_loRegClassID) | (1ull << AArch64::DDDRegClassID) | - (1ull << AArch64::DDDDRegClassID) | (1ull << AArch64::QQRegClassID) | - (1ull << AArch64::QQ_with_qsub0_in_FPR128_loRegClassID) | - (1ull << AArch64::QQ_with_qsub1_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQRegClassID) | - (1ull << AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQQRegClassID) | - (1ull << AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID) | - (1ull << AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID) | - (1ull << AArch64:: - QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID), - TRI); + setRegBankData(AArch64::FPRRegBankID, + AArch64::RegisterBankData[AArch64::FPRRegBankID], TRI); const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); (void)RBFPR; assert(&AArch64::FPRRegBank == &RBFPR && @@ -126,11 +68,8 @@ assert(RBFPR.getSize() == 512 && "FPRs should hold up to 512-bit via QQQQ sequence"); - // Initialize the CCR bank. - createRegisterBank(AArch64::CCRRegBankID, "CCR"); - setRegBankData(AArch64::CCRRegBankID, CCRData); - setRegBankCoverage(AArch64::CCRRegBankID, 1ull << AArch64::CCRRegClassID, - TRI); + setRegBankData(AArch64::CCRRegBankID, + AArch64::RegisterBankData[AArch64::CCRRegBankID], TRI); const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); (void)RBCCR; assert(&AArch64::CCRRegBank == &RBCCR &&