Index: include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -424,6 +424,8 @@
/// \todo TableGen should just generate the BitSet vector for us.
void addRegBankCoverage(unsigned ID, unsigned RCId,
const TargetRegisterInfo &TRI);
+ void setRegBankData(unsigned ID, unsigned Size);
+ void setRegBankCoverage(unsigned ID, const uint32_t *CoveredClasses);
/// Get the register bank identified by \p ID.
RegisterBank &getRegBank(unsigned ID) {
Index: lib/CodeGen/GlobalISel/RegisterBank.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBank.cpp
+++ lib/CodeGen/GlobalISel/RegisterBank.cpp
@@ -23,8 +23,6 @@
bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
assert(isValid() && "Invalid register bank");
- assert(ContainedRegClasses.size() == TRI.getNumRegClasses() &&
- "TRI does not match the initialization process?");
for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -183,6 +183,21 @@
if (!First)
DEBUG(dbgs() << '\n');
} while (!WorkList.empty());
+
+ RB.dump(&TRI);
+ llvm_unreachable("Please call setRegBankData() and setRegBankCoverage() instead");
+}
+
+void RegisterBankInfo::setRegBankData(unsigned ID, unsigned Size) {
+ RegisterBank &RB = getRegBank(ID);
+ RB.Size = Size;
+}
+
+void RegisterBankInfo::setRegBankCoverage(unsigned ID,
+ const uint32_t *CoveredClasses) {
+ RegisterBank &RB = getRegBank(ID);
+ RB.ContainedRegClasses.resize(200);
+ RB.ContainedRegClasses.setBitsInMask(CoveredClasses);
}
const RegisterBank *
Index: lib/Target/AArch64/AArch64RegisterBankInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -30,6 +30,129 @@
#error "You shouldn't build this"
#endif
+const uint32_t GPRCoverageData[] = {
+ // Classes 0-31
+ (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |
+ (1u << AArch64::GPR32spRegClassID) |
+ (1u << AArch64::GPR32commonRegClassID) |
+ (1u << AArch64::GPR32sponlyRegClassID) |
+ (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |
+ (1u << AArch64::GPR64spRegClassID) |
+ (1u << AArch64::GPR64commonRegClassID) |
+ (1u << AArch64::tcGPR64RegClassID) |
+ (1u << AArch64::GPR64sponlyRegClassID),
+ // Classes 32-63
+ 0,
+ // FIXME: The entries below this point can be safely removed once this is
+ // tablegenerated. It's only needed because of the hardcoded register class
+ // limit.
+ // Classes 64-96
+ 0,
+ // Classes 97-128
+ 0,
+ // Classes 129-160
+ 0,
+ // Classes 161-192
+ 0,
+ // Classes 193-224
+ 0,
+};
+
+const uint32_t FPRCoverageData[] = {
+ // Classes 0-31
+ (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |
+ (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |
+ (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |
+ (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |
+ (1u << AArch64::DDDDRegClassID),
+ // Classes 32-63
+ (1u << (AArch64::QQRegClassID - 32)) |
+ (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+ (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+ (1u
+ << (AArch64::
+ QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
+ 32)) |
+ (1u << (AArch64::QQQQRegClassID - 32)) |
+ (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+ (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+ (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
+ (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
+ (1u
+ << (AArch64::
+ QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
+ 32)) |
+ (1u
+ << (AArch64::
+ QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID -
+ 32)) |
+ (1u << (AArch64::QQQRegClassID - 32)) |
+ (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+ (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+ (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
+ (1u
+ << (AArch64::
+ QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID -
+ 32)),
+ // FIXME: The entries below this point can be safely removed once this
+ // is tablegenerated. It's only needed because of the hardcoded register
+ // class limit.
+ // Classes 64-96
+ 0,
+ // Classes 97-128
+ 0,
+ // Classes 129-160
+ 0,
+ // Classes 161-192
+ 0,
+ // Classes 193-224
+ 0,
+};
+
+const uint32_t CCRCoverageData[] = {
+ // Classes 0-31
+ 1u << AArch64::CCRRegClassID,
+ // Classes 32-63
+ 0,
+ // FIXME: The entries below this point can be safely removed once this
+ // is tablegenerated. It's only needed because of the hardcoded register
+ // class limit.
+ // Classes 64-96
+ 0,
+ // Classes 97-128
+ 0,
+ // Classes 129-160
+ 0,
+ // Classes 161-192
+ 0,
+ // Classes 193-224
+ 0,
+};
+
AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
: RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) {
static bool AlreadyInit = false;
@@ -45,7 +168,8 @@
createRegisterBank(AArch64::GPRRegBankID, "GPR");
// The GPR register bank is fully defined by all the registers in
// GR64all + its subclasses.
- addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
+ setRegBankData(AArch64::GPRRegBankID, 64);
+ setRegBankCoverage(AArch64::GPRRegBankID, GPRCoverageData);
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
(void)RBGPR;
assert(&AArch64::GPRRegBank == &RBGPR &&
@@ -58,7 +182,9 @@
createRegisterBank(AArch64::FPRRegBankID, "FPR");
// The FPR register bank is fully defined by all the registers in
// GR64all + its subclasses.
- addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
+ setRegBankData(AArch64::FPRRegBankID, 512);
+ setRegBankCoverage(AArch64::FPRRegBankID, FPRCoverageData);
+
const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
(void)RBFPR;
assert(&AArch64::FPRRegBank == &RBFPR &&
@@ -72,7 +198,8 @@
// Initialize the CCR bank.
createRegisterBank(AArch64::CCRRegBankID, "CCR");
- addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
+ setRegBankData(AArch64::CCRRegBankID, 32);
+ setRegBankCoverage(AArch64::CCRRegBankID, CCRCoverageData);
const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
(void)RBCCR;
assert(&AArch64::CCRRegBank == &RBCCR &&
Index: lib/Target/ARM/ARMRegisterBankInfo.cpp
===================================================================
--- lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -29,6 +29,65 @@
// into an ARMGenRegisterBankInfo.def (similar to AArch64).
namespace llvm {
namespace ARM {
+const uint32_t GPRCoverageData[] = {
+ // Classes 0-31
+ (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
+ (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
+ (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
+ (1u << ARM::GPRnopc_and_hGPRRegClassID) |
+ (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
+ (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
+ (1u << ARM::hGPR_and_tcGPRRegClassID),
+ // Classes 32-63
+ 0,
+ // Classes 64-96
+ (1u << (ARM::DQuadSpc_with_ssub_0RegClassID - 64)) |
+ (1u << (ARM::DQuadSpc_with_dsub_4_then_ssub_0RegClassID - 64)) |
+ (1u << (ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID - 64)) |
+ (1u << (ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID - 64)) |
+ (1u << (ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID - 64)) |
+ (1u << (ARM::DQuadRegClassID - 64)) |
+ (1u << (ARM::DQuad_with_ssub_0RegClassID - 64)) |
+ (1u << (ARM::DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID - 64)) |
+ (1u << (ARM::DQuad_with_dsub_1_in_DPR_8RegClassID - 64)) |
+ (1u << (ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID - 64)) |
+ (1u << (ARM::DQuad_with_dsub_2_in_DPR_8RegClassID - 64)) |
+ (1u
+ << (ARM::
+ DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID -
+ 64)) |
+ (1u << (ARM::DQuad_with_dsub_3_in_DPR_8RegClassID - 64)) |
+ (1u
+ << (ARM::
+ DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID -
+ 64)) |
+ (1u << (ARM::DQuad_with_qsub_0_in_QPR_8RegClassID - 64)) |
+ (1u << (ARM::DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID - 64)) |
+ (1u << (ARM::DQuad_with_qsub_1_in_QPR_8RegClassID - 64)) |
+ (1u
+ << (ARM::
+ DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID -
+ 64)) |
+ (1u << (ARM::QQQQPRRegClassID - 64)) |
+ (1u << (ARM::QQQQPR_with_ssub_0RegClassID - 64)) |
+ (1u << (ARM::QQQQPR_with_dsub_2_then_ssub_0RegClassID - 64)) |
+ (1u << (ARM::QQQQPR_with_dsub_7_then_ssub_0RegClassID - 64)),
+ (1u << (ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID - 96)) |
+ (1u << (ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID - 96)) |
+ (1u << (ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID - 96)),
+ // FIXME: Some of the entries below this point can be safely removed once
+ // this is tablegenerated. It's only needed because of the hardcoded
+ // register class limit.
+ // Classes 97-128
+ 0,
+ // Classes 129-160
+ 0,
+ // Classes 161-192
+ 0,
+ // Classes 193-224
+ 0,
+};
+
RegisterBank GPRRegBank;
RegisterBank *RegBanks[] = {&GPRRegBank};
@@ -53,9 +112,8 @@
// Initialize the GPR bank.
createRegisterBank(ARM::GPRRegBankID, "GPRB");
-
- addRegBankCoverage(ARM::GPRRegBankID, ARM::GPRRegClassID, TRI);
- addRegBankCoverage(ARM::GPRRegBankID, ARM::GPRwithAPSRRegClassID, TRI);
+ setRegBankData(ARM::GPRRegBankID, 32);
+ setRegBankCoverage(ARM::GPRRegBankID, ARM::GPRCoverageData);
const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
(void)RBGPR;
assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");