Index: include/llvm/CodeGen/GlobalISel/RegisterBank.h =================================================================== --- include/llvm/CodeGen/GlobalISel/RegisterBank.h +++ include/llvm/CodeGen/GlobalISel/RegisterBank.h @@ -27,10 +27,15 @@ /// Two instances of RegisterBank must have different ID. /// This property is enforced by the RegisterBankInfo class. class RegisterBank { +public: + typedef struct { + unsigned Size; + } DataTy; + private: unsigned ID; const char *Name; - unsigned Size; + DataTy Data; BitVector ContainedRegClasses; /// Sentinel value used to recognize register bank not properly @@ -55,7 +60,7 @@ const char *getName() const { return Name; } /// Get the maximal size in bits that fits in this register bank. - unsigned getSize() const { return Size; } + unsigned getSize() const { return Data.Size; } /// Check whether this instance is ready to be used. bool isValid() const; Index: include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h =================================================================== --- include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -424,6 +424,9 @@ /// \todo TableGen should just generate the BitSet vector for us. void addRegBankCoverage(unsigned ID, unsigned RCId, const TargetRegisterInfo &TRI); + void setRegBankData(unsigned ID, const RegisterBank::DataTy &Data); + void setRegBankCoverage(unsigned ID, const uint32_t *CoveredClasses, + const TargetRegisterInfo &TRI); /// Get the register bank identified by \p ID. RegisterBank &getRegBank(unsigned ID) { Index: lib/CodeGen/GlobalISel/RegisterBank.cpp =================================================================== --- lib/CodeGen/GlobalISel/RegisterBank.cpp +++ lib/CodeGen/GlobalISel/RegisterBank.cpp @@ -19,7 +19,7 @@ const unsigned RegisterBank::InvalidID = UINT_MAX; -RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {} +RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Data() {} bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { assert(isValid() && "Invalid register bank"); @@ -58,7 +58,7 @@ } bool RegisterBank::isValid() const { - return ID != InvalidID && Name != nullptr && Size != 0 && + return ID != InvalidID && Name != nullptr && getSize() != 0 && // A register bank that does not cover anything is useless. !ContainedRegClasses.empty(); } Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp =================================================================== --- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -111,7 +111,7 @@ WorkList.push_back(RCId); Covered.set(RCId); - unsigned &MaxSize = RB.Size; + unsigned &MaxSize = RB.Data.Size; do { unsigned RCId = WorkList.pop_back_val(); @@ -181,6 +181,21 @@ if (!First) DEBUG(dbgs() << '\n'); } while (!WorkList.empty()); + + llvm_unreachable("Please call setRegBankData() and setRegBankCoverage() instead"); +} + +void RegisterBankInfo::setRegBankData(unsigned ID, const RegisterBank::DataTy &Data) { + RegisterBank &RB = getRegBank(ID); + RB.Data = Data; +} + +void RegisterBankInfo::setRegBankCoverage(unsigned ID, + const uint32_t *CoveredClasses, + const TargetRegisterInfo &TRI) { + RegisterBank &RB = getRegBank(ID); + RB.ContainedRegClasses.resize(TRI.getNumRegClasses()); + RB.ContainedRegClasses.setBitsInMask(CoveredClasses); } const RegisterBank * Index: lib/Target/AArch64/AArch64RegisterBankInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -30,6 +30,82 @@ #error "You shouldn't build this" #endif +const RegisterBank::DataTy GPRData = {64}; +const RegisterBank::DataTy FPRData = {512}; +const RegisterBank::DataTy CCRData = {32}; + +const uint32_t GPRCoverageData[] = { + (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) | + (1u << AArch64::GPR32spRegClassID) | + (1u << AArch64::GPR32commonRegClassID) | + (1u << AArch64::GPR32sponlyRegClassID) | + (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) | + (1u << AArch64::GPR64spRegClassID) | + (1u << AArch64::GPR64commonRegClassID) | + (1u << AArch64::tcGPR64RegClassID) | + (1u << AArch64::GPR64sponlyRegClassID), + 0, +}; +const uint32_t FPRCoverageData[] = { + (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) | + (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) | + (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) | + (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) | + (1u << AArch64::DDDDRegClassID), + (1u << (AArch64::QQRegClassID - 32)) | + (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) | + (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) | + (1u + << (AArch64:: + QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - + 32)) | + (1u << (AArch64::QQQQRegClassID - 32)) | + (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) | + (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) | + (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) | + (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) | + (1u + << (AArch64:: + QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - + 32)) | + (1u + << (AArch64:: + QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - + 32)) | + (1u << (AArch64::QQQRegClassID - 32)) | + (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) | + (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) | + (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) | + (1u + << (AArch64:: + QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - + 32))}; +const uint32_t CCRCoverageData[] = {1u << AArch64::CCRRegClassID, 0}; + AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) : RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) { static bool AlreadyInit = false; @@ -45,7 +121,9 @@ createRegisterBank(AArch64::GPRRegBankID, "GPR"); // The GPR register bank is fully defined by all the registers in // GR64all + its subclasses. - addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI); + setRegBankData(AArch64::GPRRegBankID, GPRData); + setRegBankCoverage(AArch64::GPRRegBankID, GPRCoverageData, + TRI); const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); (void)RBGPR; assert(&AArch64::GPRRegBank == &RBGPR && @@ -58,7 +136,8 @@ createRegisterBank(AArch64::FPRRegBankID, "FPR"); // The FPR register bank is fully defined by all the registers in // GR64all + its subclasses. - addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI); + setRegBankData(AArch64::FPRRegBankID, FPRData); + setRegBankCoverage(AArch64::FPRRegBankID, FPRCoverageData, TRI); const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); (void)RBFPR; assert(&AArch64::FPRRegBank == &RBFPR && @@ -72,7 +151,8 @@ // Initialize the CCR bank. createRegisterBank(AArch64::CCRRegBankID, "CCR"); - addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI); + setRegBankData(AArch64::CCRRegBankID, CCRData); + setRegBankCoverage(AArch64::CCRRegBankID, CCRCoverageData, TRI); const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); (void)RBCCR; assert(&AArch64::CCRRegBank == &RBCCR && Index: lib/Target/ARM/ARMRegisterBankInfo.cpp =================================================================== --- lib/Target/ARM/ARMRegisterBankInfo.cpp +++ lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -29,6 +29,52 @@ // into an ARMGenRegisterBankInfo.def (similar to AArch64). namespace llvm { namespace ARM { +const RegisterBank::DataTy GPRData = {32}; +const uint32_t GPRCoverageData[] = { + (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) | + (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) | + (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) | + (1u << ARM::GPRnopc_and_hGPRRegClassID) | + (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) | + (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) | + (1u << ARM::hGPR_and_tcGPRRegClassID), + 0, + (1u << (ARM::DQuadSpc_with_ssub_0RegClassID - 64)) | + (1u << (ARM::DQuadSpc_with_dsub_4_then_ssub_0RegClassID - 64)) | + (1u << (ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID - 64)) | + (1u << (ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID - 64)) | + (1u << (ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID - 64)) | + (1u << (ARM::DQuadRegClassID - 64)) | + (1u << (ARM::DQuad_with_ssub_0RegClassID - 64)) | + (1u << (ARM::DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID - 64)) | + (1u << (ARM::DQuad_with_dsub_1_in_DPR_8RegClassID - 64)) | + (1u << (ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID - 64)) | + (1u << (ARM::DQuad_with_dsub_2_in_DPR_8RegClassID - 64)) | + (1u + << (ARM:: + DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID - + 64)) | + (1u << (ARM::DQuad_with_dsub_3_in_DPR_8RegClassID - 64)) | + (1u + << (ARM:: + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID - + 64)) | + (1u << (ARM::DQuad_with_qsub_0_in_QPR_8RegClassID - 64)) | + (1u << (ARM::DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID - 64)) | + (1u << (ARM::DQuad_with_qsub_1_in_QPR_8RegClassID - 64)) | + (1u + << (ARM:: + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID - + 64)) | + (1u << (ARM::QQQQPRRegClassID - 64)) | + (1u << (ARM::QQQQPR_with_ssub_0RegClassID - 64)) | + (1u << (ARM::QQQQPR_with_dsub_2_then_ssub_0RegClassID - 64)) | + (1u << (ARM::QQQQPR_with_dsub_7_then_ssub_0RegClassID - 64)), + (1u << (ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID - 96)) | + (1u << (ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID - 96)) | + (1u << (ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID - 96)), +}; + RegisterBank GPRRegBank; RegisterBank *RegBanks[] = {&GPRRegBank}; @@ -53,9 +99,8 @@ // Initialize the GPR bank. createRegisterBank(ARM::GPRRegBankID, "GPRB"); - - addRegBankCoverage(ARM::GPRRegBankID, ARM::GPRRegClassID, TRI); - addRegBankCoverage(ARM::GPRRegBankID, ARM::GPRwithAPSRRegClassID, TRI); + setRegBankData(ARM::GPRRegBankID, ARM::GPRData); + setRegBankCoverage(ARM::GPRRegBankID, ARM::GPRCoverageData, TRI); const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); (void)RBGPR; assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");