Index: lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- lib/Target/AMDGPU/VOP2Instructions.td
+++ lib/Target/AMDGPU/VOP2Instructions.td
@@ -340,7 +340,7 @@
 def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>;
 defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
 defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
-defm V_ASHRREV_B16 : VOP2Inst <"v_ashrrev_b16", VOP_I16_I16_I16>;
+defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>;
 defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
 
 let isCommutable = 1 in {
@@ -443,7 +443,7 @@
 
 defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
 defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;
-defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_B16_e32>;
+defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e32>;
 
 def : ZExt_i16_i1_Pat<zext>;
 def : ZExt_i16_i1_Pat<anyext>;
@@ -689,7 +689,7 @@
 defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
 defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
 defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
-defm V_ASHRREV_B16        : VOP2_Real_e32e64_vi <0x2c>;
+defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
 defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
 defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
 defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
Index: test/MC/AMDGPU/vop2.s
===================================================================
--- test/MC/AMDGPU/vop2.s
+++ test/MC/AMDGPU/vop2.s
@@ -461,9 +461,9 @@
 v_lshrrev_b16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_ashrrev_b16_e32 v1, v2, v3
-// VI:     v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
-v_ashrrev_b16_e32 v1, v2, v3
+// NOSICI: v_ashrrev_i16_e32 v1, v2, v3
+// VI:     v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
+v_ashrrev_i16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
 // NOSICI: v_max_f16_e32 v1, v2, v3
Index: test/MC/AMDGPU/vop3-convert.s
===================================================================
--- test/MC/AMDGPU/vop3-convert.s
+++ test/MC/AMDGPU/vop3-convert.s
@@ -371,9 +371,9 @@
 v_lshrrev_b16 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_ashrrev_b16 v1, v2, v3
-// VI:     v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
-v_ashrrev_b16 v1, v2, v3
+// NOSICI: v_ashrrev_i16 v1, v2, v3
+// VI:     v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
+v_ashrrev_i16 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
 // NOSICI: v_max_f16 v1, v2, v3
Index: test/MC/AMDGPU/vop_sdwa.s
===================================================================
--- test/MC/AMDGPU/vop_sdwa.s
+++ test/MC/AMDGPU/vop_sdwa.s
@@ -481,8 +481,8 @@
 v_lshrrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
 
 // NOSICI: error:
-// VI: v_ashrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02]
-v_ashrrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+// VI: v_ashrrev_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02]
+v_ashrrev_i16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
 
 // NOSICI: error:
 // VI: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02]
Index: test/MC/Disassembler/AMDGPU/sdwa_vi.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/sdwa_vi.txt
+++ test/MC/Disassembler/AMDGPU/sdwa_vi.txt
@@ -321,7 +321,7 @@
 # VI: v_lshrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x56,0x02,0x06,0x05,0x02]
 0xf9 0x06 0x02 0x56 0x02 0x06 0x05 0x02
 
-# VI: v_ashrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02]
+# VI: v_ashrrev_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02]
 0xf9 0x06 0x02 0x58 0x02 0x06 0x05 0x02
 
 # VI: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02]
Index: test/MC/Disassembler/AMDGPU/vop2_vi.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/vop2_vi.txt
+++ test/MC/Disassembler/AMDGPU/vop2_vi.txt
@@ -231,7 +231,7 @@
 # VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
 0x02 0x07 0x02 0x56
 
-# VI:     v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
+# VI:     v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
 0x02 0x07 0x02 0x58
 
 # VI:     v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]