Index: lib/Target/ARM/ARMCallLowering.cpp
===================================================================
--- lib/Target/ARM/ARMCallLowering.cpp
+++ lib/Target/ARM/ARMCallLowering.cpp
@@ -38,7 +38,7 @@
     return false;
 
   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
-  return VTSize == 8 || VTSize == 16 || VTSize == 32;
+  return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
 }
 
 namespace {
Index: lib/Target/ARM/ARMInstructionSelector.cpp
===================================================================
--- lib/Target/ARM/ARMInstructionSelector.cpp
+++ lib/Target/ARM/ARMInstructionSelector.cpp
@@ -101,10 +101,13 @@
   }
 
   MachineInstrBuilder MIB{MF, I};
+  bool isSExt = false;
 
   using namespace TargetOpcode;
   switch (I.getOpcode()) {
   case G_SEXT:
+    isSExt = true;
+    LLVM_FALLTHROUGH;
   case G_ZEXT: {
     LLT DstTy = MRI.getType(I.getOperand(0).getReg());
     // FIXME: Smaller destination sizes coming soon!
@@ -116,11 +119,36 @@
     LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
     unsigned SrcSize = SrcTy.getSizeInBits();
     switch (SrcSize) {
+    case 1: {
+      // ZExt boils down to & 0x1; for SExt we also subtract that from 0
+      I.setDesc(TII.get(ARM::ANDri));
+      MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
+
+      if (isSExt) {
+        unsigned SExtResult = I.getOperand(0).getReg();
+
+        // Use a new virtual register for the result of the AND
+        unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
+        I.getOperand(0).setReg(AndResult);
+
+        auto InsertBefore = std::next(I.getIterator());
+        auto &SubI =
+            BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
+                .addDef(SExtResult)
+                .addUse(AndResult)
+                .addImm(0)
+                .add(predOps(ARMCC::AL))
+                .add(condCodeOp());
+        if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
+          return false;
+      }
+      break;
+    }
     case 8:
     case 16: {
       unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
       I.setDesc(TII.get(NewOpc));
-      AddDefaultPred(MIB.addImm(0));
+      MIB.addImm(0).add(predOps(ARMCC::AL));
       break;
     }
     default:
Index: lib/Target/ARM/ARMLegalizerInfo.cpp
===================================================================
--- lib/Target/ARM/ARMLegalizerInfo.cpp
+++ lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -28,6 +28,7 @@
 
   const LLT p0 = LLT::pointer(0, 32);
 
+  const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
@@ -37,12 +38,12 @@
   setAction({G_LOAD, s32}, Legal);
   setAction({G_LOAD, 1, p0}, Legal);
 
-  for (auto Ty : {s8, s16, s32})
+  for (auto Ty : {s1, s8, s16, s32})
     setAction({G_ADD, Ty}, Legal);
 
   for (auto Op : {G_SEXT, G_ZEXT}) {
     setAction({Op, s32}, Legal);
-    for (auto Ty : {s8, s16})
+    for (auto Ty : {s1, s8, s16})
       setAction({Op, 1, Ty}, Legal);
   }
 
Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -1,5 +1,7 @@
 # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 --- |
+  define void @test_zext_s1() { ret void }
+  define void @test_sext_s1() { ret void }
   define void @test_sext_s8() { ret void }
   define void @test_zext_s16() { ret void }
 
@@ -10,6 +12,59 @@
   define void @test_load_from_stack() { ret void }
 ...
 ---
+name:            test_zext_s1
+# CHECK-LABEL: name: test_zext_s1
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s1) = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+    %1(s32) = G_ZEXT %0(s1)
+    ; CHECK: [[VREGEXT:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
+
+    %r0 = COPY %1(s32)
+    ; CHECK: %r0 = COPY [[VREGEXT]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name:            test_sext_s1
+# CHECK-LABEL: name: test_sext_s1
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s1) = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+    %1(s32) = G_SEXT %0(s1)
+    ; CHECK: [[VREGAND:%[0-9]+]] = ANDri [[VREGX]], 1, 14, _, _
+    ; CHECK: [[VREGEXT:%[0-9]+]] = RSBri [[VREGAND]], 0, 14, _, _
+
+    %r0 = COPY %1(s32)
+    ; CHECK: %r0 = COPY [[VREGEXT]]
+
+    BX_RET 14, _, implicit %r0
+    ; CHECK: BX_RET 14, _, implicit %r0
+...
 ---
 name:            test_sext_s8
 # CHECK-LABEL: name: test_sext_s8
Index: test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -7,6 +7,20 @@
   ret void
 }
 
+define signext i1 @test_add_i1(i1 %x, i1 %y) {
+; CHECK-LABEL: name: test_add_i1
+; CHECK: liveins: %r0, %r1
+; CHECK-DAG: [[VREGX:%[0-9]+]](s1) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s1) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s1) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: [[EXT:%[0-9]+]](s32) = G_SEXT [[SUM]]
+; CHECK: %r0 = COPY [[EXT]](s32)
+; CHECK: BX_RET 14, _, implicit %r0
+entry:
+  %sum = add i1 %x, %y
+  ret i1 %sum
+}
+
 define i8 @test_add_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: name: test_add_i8
 ; CHECK: liveins: %r0, %r1
Index: test/CodeGen/ARM/GlobalISel/arm-isel.ll
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-isel.ll
+++ test/CodeGen/ARM/GlobalISel/arm-isel.ll
@@ -7,6 +7,23 @@
   ret void
 }
 
+define zeroext i1 @test_zext_i1(i1 %x) {
+; CHECK-LABEL: test_zext_i1
+; CHECK: and r0, r0, #1
+; CHECK: bx lr
+entry:
+  ret i1 %x
+}
+
+define signext i1 @test_sext_i1(i1 %x) {
+; CHECK-LABEL: test_sext_i1
+; CHECK: and r0, r0, #1
+; CHECK: rsb r0, r0, #0
+; CHECK: bx lr
+entry:
+  ret i1 %x
+}
+
 define zeroext i8 @test_ext_i8(i8 %x) {
 ; CHECK-LABEL: test_ext_i8:
 ; CHECK: uxtb r0, r0
Index: test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
===================================================================
--- test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -3,6 +3,7 @@
   define void @test_add_s32() { ret void }
   define void @test_add_s16() { ret void }
   define void @test_add_s8() { ret void }
+  define void @test_add_s1() { ret void }
 ...
 ---
 name:            test_add_s32
@@ -82,3 +83,29 @@
     BX_RET 14, _, implicit %r0
 
 ...
+---
+name:            test_add_s1
+# CHECK-LABEL: name: test_add_s1
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s1) = COPY %r0
+    %1(s1) = COPY %r1
+    %2(s1) = G_ADD %0, %1
+    %r0 = COPY %2(s1)
+    BX_RET 14, _, implicit %r0
+
+...