AMDGPU: Fix vintrp disassembly

[• tstellarAMD]

LGTM.

[arsenm]

r289292

lib/Target/AMDGPU/SIInstrFormats.td

class EXPe : Enc64 {
   let Inst{55-48} = vsrc2;
   let Inst{63-56} = vsrc3;
 }
 
 let Uses = [EXEC] in {
 
 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
-
+  let VINTRP = 1;
   // VINTRP instructions read parameter values from LDS, but these parameter
   // values are stored outside of the LDS memory that is allocated to the
   // shader for general purpose use.
   //
   // While it may be possible for ds_read/ds_write instructions to access
   // the parameter values in LDS, this would essentially be an out-of-bounds
   // memory access which we consider to be undefined behavior.
   //

lib/Target/AMDGPU/SIInstructions.td

 
 let Uses = [M0, EXEC] in {
 
 // FIXME: Specify SchedRW for VINTRP insturctions.
 
 multiclass V_INTERP_P1_F32_m : VINTRP_m <
   0x00000000,
   (outs VGPR_32:$vdst),
-  (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
-  "v_interp_p1_f32 $vdst, $i, $attr_chan, $attr",
-  [(set f32:$vdst, (AMDGPUinterp_p1 f32:$i, (i32 imm:$attr_chan),
+  (ins VGPR_32:$vsrc, i32imm:$attrchan, i32imm:$attr),
+  "v_interp_p1_f32 $vdst, $vsrc, $attrchan, $attr",
+  [(set f32:$vdst, (AMDGPUinterp_p1 f32:$vsrc, (i32 imm:$attrchan),
                                                (i32 imm:$attr)))]
 >;
 
 let OtherPredicates = [has32BankLDS] in {
 
 defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
 
 } // End OtherPredicates = [has32BankLDS]
 
 let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
 
 defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
 
 } // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
 
 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
 
 defm V_INTERP_P2_F32 : VINTRP_m <
   0x00000001,
   (outs VGPR_32:$vdst),
-  (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
-  "v_interp_p2_f32 $vdst, $j, $attr_chan, $attr",
-  [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$j, (i32 imm:$attr_chan),
+  (ins VGPR_32:$src0, VGPR_32:$vsrc, i32imm:$attrchan, i32imm:$attr),
+  "v_interp_p2_f32 $vdst, $vsrc, $attrchan, $attr",
+  [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$vsrc, (i32 imm:$attrchan),
                                                           (i32 imm:$attr)))]>;
 
 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
 
 defm V_INTERP_MOV_F32 : VINTRP_m <
   0x00000002,
   (outs VGPR_32:$vdst),
-  (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
-  "v_interp_mov_f32 $vdst, $src0, $attr_chan, $attr",
-  [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
+  (ins InterpSlot:$vsrc, i32imm:$attrchan, i32imm:$attr),
+  "v_interp_mov_f32 $vdst, $vsrc, $attrchan, $attr",
+  [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 imm:$attrchan),
                                      (i32 imm:$attr)))]>;
 
 } // End Uses = [M0, EXEC]
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 

test/MC/Disassembler/AMDGPU/missing_op.txt

-# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI
-
-#TODO: this test will fail when we fix v_interp_p2_f32 signature, remove it then
-#VI: v_interp_p2_f32 v7, 16, /*Missing OP3*/, /*Missing OP4*/
-0xd4 0x41 0x1d 0xd4

test/MC/Disassembler/AMDGPU/vintrp.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI
+
+#VI: v_interp_p1_f32 v7, v212, 1, 16
+0xd4 0x41 0x1c 0xd4
+
+#VI: v_interp_p2_f32 v7, v212, 1, 16
+0xd4 0x41 0x1d 0xd4
+
+#VI: v_interp_mov_f32 v7, invalid_param_212, 1, 16
+0xd4 0x41 0x1e 0xd4
+
+#VI: v_interp_mov_f32 v7, p10, 1, 16
+0x00 0x41 0x1e 0xd4
+
+#VI: v_interp_mov_f32 v7, p20, 1, 16
+0x01 0x41 0x1e 0xd4
+
+#VI: v_interp_mov_f32 v7, p0, 1, 16
+0x02 0x41 0x1e 0xd4
+
+#VI: v_interp_mov_f32 v7, invalid_param_3, 1, 16
+0x03 0x41 0x1e 0xd4
+
+# VI: v_interp_p1_f32 v0, v0, 0, 0
+0x00 0x00 0x00 0xd4
+
+# VI: v_interp_p1_f32 v0, v0, 0, 0
+0x00 0x00 0x00 0xd4
+
+# VI: v_interp_p1_f32 v0, v1, 0, 0
+0x01 0x00 0x00 0xd4
+
+# VI: v_interp_p1_f32 v0, v1, 3, 0
+0x01 0x03 0x00 0xd4
+
+# VI: v_interp_p2_f32 v0, v1, 0, 0
+0x01 0x00 0x01 0xd4
+
+# VI: v_interp_mov_f32 v0, p20, 0, 0
+0x01 0x00 0x02 0xd4
+
+#VI: v_interp_p2_f32 v0, v1, 0, 63
+0x01 0xfc 0x01 0xd4
+
+#VI: v_interp_p2_f32 v0, v1, 0, 63
+0x01 0xfc 0x01 0xd4
+
+#VI: v_interp_p2_f32 v0, v1, 3, 63
+0x01 0xff 0x01 0xd4