Index: include/llvm/CodeGen/MachineBasicBlock.h =================================================================== --- include/llvm/CodeGen/MachineBasicBlock.h +++ include/llvm/CodeGen/MachineBasicBlock.h @@ -307,7 +307,7 @@ // Iteration support for live in sets. These sets are kept in sorted // order by their register number. typedef LiveInVector::const_iterator livein_iterator; - livein_iterator livein_begin() const { return LiveIns.begin(); } + livein_iterator livein_begin() const; livein_iterator livein_end() const { return LiveIns.end(); } bool livein_empty() const { return LiveIns.empty(); } iterator_range liveins() const { Index: lib/CodeGen/IfConversion.cpp =================================================================== --- lib/CodeGen/IfConversion.cpp +++ lib/CodeGen/IfConversion.cpp @@ -1515,16 +1515,18 @@ if (TII->reverseBranchCondition(Cond)) llvm_unreachable("Unable to reverse branch condition!"); - // Initialize liveins to the first BB. These are potentiall redefined by - // predicated instructions. Redefs.init(*TRI); - Redefs.addLiveIns(CvtMBB); - Redefs.addLiveIns(NextMBB); - - // Compute a set of registers which must not be killed by instructions in - // BB1: This is everything live-in to BB2. DontKill.init(*TRI); - DontKill.addLiveIns(NextMBB); + + if (MRI->tracksLiveness()) { + // Initialize liveins to the first BB. These are potentiall redefined by + // predicated instructions. + Redefs.addLiveIns(CvtMBB); + Redefs.addLiveIns(NextMBB); + // Compute a set of registers which must not be killed by instructions in + // BB1: This is everything live-in to BB2. + DontKill.addLiveIns(NextMBB); + } if (CvtMBB.pred_size() > 1) { BBI.NonPredSize -= TII->removeBranch(*BBI.BB); @@ -1622,8 +1624,10 @@ // Initialize liveins to the first BB. These are potentially redefined by // predicated instructions. Redefs.init(*TRI); - Redefs.addLiveIns(CvtMBB); - Redefs.addLiveIns(NextMBB); + if (MRI->tracksLiveness()) { + Redefs.addLiveIns(CvtMBB); + Redefs.addLiveIns(NextMBB); + } DontKill.clear(); @@ -1786,8 +1790,10 @@ // instructions. We start with BB1 live-ins so we have the live-out regs // after tracking the BB1 instructions. Redefs.init(*TRI); - Redefs.addLiveIns(MBB1); - Redefs.addLiveIns(MBB2); + if (MRI->tracksLiveness()) { + Redefs.addLiveIns(MBB1); + Redefs.addLiveIns(MBB2); + } // Remove the duplicated instructions at the beginnings of both paths. // Skip dbg_value instructions @@ -1812,12 +1818,14 @@ // This is everything used+live in BB2 after the duplicated instructions. We // can compute this set by simulating liveness backwards from the end of BB2. DontKill.init(*TRI); - for (const MachineInstr &MI : make_range(MBB2.rbegin(), ++DI2.getReverse())) - DontKill.stepBackward(MI); + if (MRI->tracksLiveness()) { + for (const MachineInstr &MI : make_range(MBB2.rbegin(), ++DI2.getReverse())) + DontKill.stepBackward(MI); - for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) { - SmallVector, 4> IgnoredClobbers; - Redefs.stepForward(MI, IgnoredClobbers); + for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) { + SmallVector, 4> Dummy; + Redefs.stepForward(MI, Dummy); + } } BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1); MBB2.erase(MBB2.begin(), DI2); Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -488,16 +488,16 @@ } // Print the live in registers. - const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo(); - assert(TRI && "Expected target register info"); - if (!MBB.livein_empty()) { + const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + if (MRI.tracksLiveness() && !MBB.livein_empty()) { + const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); OS.indent(2) << "liveins: "; bool First = true; for (const auto &LI : MBB.liveins()) { if (!First) OS << ", "; First = false; - printReg(LI.PhysReg, OS, TRI); + printReg(LI.PhysReg, OS, &TRI); if (LI.LaneMask != ~0u) OS << ":0x" << PrintLaneMask(LI.LaneMask); } Index: lib/CodeGen/MachineBasicBlock.cpp =================================================================== --- lib/CodeGen/MachineBasicBlock.cpp +++ lib/CodeGen/MachineBasicBlock.cpp @@ -1301,3 +1301,10 @@ void MachineBasicBlock::clearLiveIns() { LiveIns.clear(); } + +MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const { + assert(getParent()->getProperties().hasProperty( + MachineFunctionProperties::Property::TracksLiveness) && + "Liveness information is accurate"); + return LiveIns.begin(); +} Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -565,7 +565,7 @@ FirstTerminator = nullptr; if (!MF->getProperties().hasProperty( - MachineFunctionProperties::Property::NoPHIs)) { + MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) { // If this block has allocatable physical registers live-in, check that // it is an entry block or landing pad. for (const auto &LI : MBB->liveins()) { @@ -740,14 +740,16 @@ } regsLive.clear(); - for (const auto &LI : MBB->liveins()) { - if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) { - report("MBB live-in list contains non-physical register", MBB); - continue; + if (MRI->tracksLiveness()) { + for (const auto &LI : MBB->liveins()) { + if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) { + report("MBB live-in list contains non-physical register", MBB); + continue; + } + for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true); + SubRegs.isValid(); ++SubRegs) + regsLive.insert(*SubRegs); } - for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true); - SubRegs.isValid(); ++SubRegs) - regsLive.insert(*SubRegs); } regsLiveInButUnused = regsLive; Index: lib/CodeGen/RegisterScavenging.cpp =================================================================== --- lib/CodeGen/RegisterScavenging.cpp +++ lib/CodeGen/RegisterScavenging.cpp @@ -48,11 +48,6 @@ assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && "Target changed?"); - // It is not possible to use the register scavenger after late optimization - // passes that don't preserve accurate liveness information. - assert(MRI->tracksLiveness() && - "Cannot use register scavenger with inaccurate liveness"); - // Self-initialize. if (!this->MBB) { NumRegUnits = TRI->getNumRegUnits(); Index: test/CodeGen/AArch64/machine-scheduler.mir =================================================================== --- test/CodeGen/AArch64/machine-scheduler.mir +++ test/CodeGen/AArch64/machine-scheduler.mir @@ -21,8 +21,9 @@ # CHECK: LDRWui %x0, 0 # CHECK: LDRWui %x0, 1 # CHECK: STRWui %w1, %x0, 2 -name: load_imp-def -body: | +name: load_imp-def +tracksRegLiveness: true +body: | bb.0.entry: liveins: %w1, %x0 %w8 = LDRWui %x0, 1, implicit-def %x8 :: (load 4 from %ir.0) Index: test/CodeGen/MIR/X86/basic-block-liveins.mir =================================================================== --- test/CodeGen/MIR/X86/basic-block-liveins.mir +++ test/CodeGen/MIR/X86/basic-block-liveins.mir @@ -22,7 +22,8 @@ ... --- -name: test +name: test +tracksRegLiveness: true body: | ; CHECK-LABEL: bb.0.body: ; CHECK-NEXT: liveins: %edi, %esi @@ -33,7 +34,8 @@ RETQ %eax ... --- -name: test2 +name: test2 +tracksRegLiveness: true body: | ; CHECK-LABEL: name: test2 ; Verify that we can have multiple lists of liveins that will be merged into @@ -48,7 +50,8 @@ RETQ %eax ... --- -name: test3 +name: test3 +tracksRegLiveness: true body: | ; Verify that we can have an empty list of liveins. ; CHECK-LABEL: name: test3 Index: test/CodeGen/MIR/X86/machine-verifier.mir =================================================================== --- test/CodeGen/MIR/X86/machine-verifier.mir +++ test/CodeGen/MIR/X86/machine-verifier.mir @@ -10,7 +10,8 @@ ... --- -name: inc +name: inc +tracksRegLiveness: true body: | bb.0.entry: liveins: %edi Index: test/CodeGen/X86/tail-call-conditional.mir =================================================================== --- test/CodeGen/X86/tail-call-conditional.mir +++ test/CodeGen/X86/tail-call-conditional.mir @@ -26,7 +26,8 @@ ... --- -name: test +name: test +tracksRegLiveness: true liveins: - { reg: '%rdi' } - { reg: '%rsi' }