Index: lib/Target/AMDGPU/SIDefines.h =================================================================== --- lib/Target/AMDGPU/SIDefines.h +++ lib/Target/AMDGPU/SIDefines.h @@ -13,45 +13,78 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H +namespace llvm { + namespace SIInstrFlags { // This needs to be kept in sync with the field bits in InstSI. -enum : uint32_t { - SALU = 1 << 3, - VALU = 1 << 4, - - SOP1 = 1 << 5, - SOP2 = 1 << 6, - SOPC = 1 << 7, - SOPK = 1 << 8, - SOPP = 1 << 9, - - VOP1 = 1 << 10, - VOP2 = 1 << 11, - VOP3 = 1 << 12, - VOPC = 1 << 13, +enum : uint64_t { + // Low bits - basic encoding information. + SALU = 1 << 0, + VALU = 1 << 1, + + // SALU instruction formats. + SOP1 = 1 << 2, + SOP2 = 1 << 3, + SOPC = 1 << 4, + SOPK = 1 << 5, + SOPP = 1 << 6, + + // VALU instruction formats. + VOP1 = 1 << 7, + VOP2 = 1 << 8, + VOPC = 1 << 9, + + // TODO: Should this be spilt into VOP3 a and b? + VOP3 = 1 << 10, + + VINTRP = 1 << 13, SDWA = 1 << 14, DPP = 1 << 15, + // Memory instruction formats. MUBUF = 1 << 16, MTBUF = 1 << 17, SMRD = 1 << 18, - DS = 1 << 19, - MIMG = 1 << 20, + MIMG = 1 << 19, + EXP = 1 << 20, FLAT = 1 << 21, - EXP = 1 << 22, - WQM = 1 << 23, - VGPRSpill = 1 << 24, - SGPRSpill = 1 << 25, - VOPAsmPrefer32Bit = 1 << 26, - Gather4 = 1 << 27, - DisableWQM = 1 << 28, - SOPK_ZEXT = 1 << 29, - SCALAR_STORE = 1 << 30, - FIXED_SIZE = 1u << 31 + DS = 1 << 22, + + // Pseudo instruction formats. + VGPRSpill = 1 << 23, + SGPRSpill = 1 << 24, + + // High bits - other information. + VM_CNT = UINT64_C(1) << 32, + EXP_CNT = UINT64_C(1) << 33, + LGKM_CNT = UINT64_C(1) << 34, + + WQM = UINT64_C(1) << 35, + DisableWQM = UINT64_C(1) << 36, + Gather4 = UINT64_C(1) << 37, + SOPK_ZEXT = UINT64_C(1) << 38, + SCALAR_STORE = UINT64_C(1) << 39, + FIXED_SIZE = UINT64_C(1) << 40, + VOPAsmPrefer32Bit = UINT64_C(1) << 41 + +}; + +// v_cmp_class_* etc. use a 10-bit mask for what operation is checked. +// The result is true if any of these tests are true. +enum ClassFlags { + S_NAN = 1 << 0, // Signaling NaN + Q_NAN = 1 << 1, // Quiet NaN + N_INFINITY = 1 << 2, // Negative infinity + N_NORMAL = 1 << 3, // Negative normal + N_SUBNORMAL = 1 << 4, // Negative subnormal + N_ZERO = 1 << 5, // Negative zero + P_ZERO = 1 << 6, // Positive zero + P_SUBNORMAL = 1 << 7, // Positive subnormal + P_NORMAL = 1 << 8, // Positive normal + P_INFINITY = 1 << 9 // Positive infinity }; } -namespace llvm { namespace AMDGPU { enum OperandType { /// Operands with register or 32-bit immediate @@ -68,31 +101,6 @@ OPERAND_KIMM32 }; } -} - -namespace SIInstrFlags { - enum Flags { - // First 4 bits are the instruction encoding - VM_CNT = 1 << 0, - EXP_CNT = 1 << 1, - LGKM_CNT = 1 << 2 - }; - - // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. - // The result is true if any of these tests are true. - enum ClassFlags { - S_NAN = 1 << 0, // Signaling NaN - Q_NAN = 1 << 1, // Quiet NaN - N_INFINITY = 1 << 2, // Negative infinity - N_NORMAL = 1 << 3, // Negative normal - N_SUBNORMAL = 1 << 4, // Negative subnormal - N_ZERO = 1 << 5, // Negative zero - P_ZERO = 1 << 6, // Positive zero - P_SUBNORMAL = 1 << 7, // Positive subnormal - P_NORMAL = 1 << 8, // Positive normal - P_INFINITY = 1 << 9 // Positive infinity - }; -} // Input operand modifiers bit-masks // NEG and SEXT share same bit-mask because they can't be set simultaneously. @@ -131,7 +139,6 @@ }; } -namespace llvm { namespace AMDGPU { namespace EncValues { // Encoding values of enum9/8/7 operands @@ -152,9 +159,7 @@ } // namespace EncValues } // namespace AMDGPU -} // namespace llvm -namespace llvm { namespace AMDGPU { namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. @@ -259,7 +264,6 @@ } // namespace SDWA } // namespace AMDGPU -} // namespace llvm #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C @@ -365,4 +369,6 @@ #define R_SPILLED_SGPRS 0x4 #define R_SPILLED_VGPRS 0x8 +} // End namespace llvm + #endif Index: lib/Target/AMDGPU/SIInstrFormats.td =================================================================== --- lib/Target/AMDGPU/SIInstrFormats.td +++ lib/Target/AMDGPU/SIInstrFormats.td @@ -15,48 +15,52 @@ list pattern = []> : AMDGPUInst, PredicateControl { - field bit VM_CNT = 0; - field bit EXP_CNT = 0; - field bit LGKM_CNT = 0; - + // Low bits - basic encoding information. field bit SALU = 0; field bit VALU = 0; + // SALU instruction formats. field bit SOP1 = 0; field bit SOP2 = 0; field bit SOPC = 0; field bit SOPK = 0; field bit SOPP = 0; + // VALU instruction formats. field bit VOP1 = 0; field bit VOP2 = 0; - field bit VOP3 = 0; field bit VOPC = 0; + field bit VOP3 = 0; + field bit VINTRP = 0; field bit SDWA = 0; field bit DPP = 0; + // Memory instruction formats. field bit MUBUF = 0; field bit MTBUF = 0; field bit SMRD = 0; - field bit DS = 0; field bit MIMG = 0; - field bit FLAT = 0; field bit EXP = 0; + field bit FLAT = 0; + field bit DS = 0; - // Whether WQM _must_ be enabled for this instruction. - field bit WQM = 0; + // Pseudo instruction formats. field bit VGPRSpill = 0; field bit SGPRSpill = 0; - // This bit tells the assembler to use the 32-bit encoding in case it - // is unable to infer the encoding from the operands. - field bit VOPAsmPrefer32Bit = 0; + // High bits - other information. + field bit VM_CNT = 0; + field bit EXP_CNT = 0; + field bit LGKM_CNT = 0; - field bit Gather4 = 0; + // Whether WQM _must_ be enabled for this instruction. + field bit WQM = 0; // Whether WQM _must_ be disabled for this instruction. field bit DisableWQM = 0; + field bit Gather4 = 0; + // Most sopk treat the immediate as a signed 16-bit, however some // use it as unsigned. field bit SOPKZext = 0; @@ -70,43 +74,52 @@ // instruction size. field bit FixedSize = 0; + // This bit tells the assembler to use the 32-bit encoding in case it + // is unable to infer the encoding from the operands. + field bit VOPAsmPrefer32Bit = 0; + // These need to be kept in sync with the enum in SIInstrFlags. - let TSFlags{0} = VM_CNT; - let TSFlags{1} = EXP_CNT; - let TSFlags{2} = LGKM_CNT; - - let TSFlags{3} = SALU; - let TSFlags{4} = VALU; - - let TSFlags{5} = SOP1; - let TSFlags{6} = SOP2; - let TSFlags{7} = SOPC; - let TSFlags{8} = SOPK; - let TSFlags{9} = SOPP; - - let TSFlags{10} = VOP1; - let TSFlags{11} = VOP2; - let TSFlags{12} = VOP3; - let TSFlags{13} = VOPC; + let TSFlags{0} = SALU; + let TSFlags{1} = VALU; + + let TSFlags{2} = SOP1; + let TSFlags{3} = SOP2; + let TSFlags{4} = SOPC; + let TSFlags{5} = SOPK; + let TSFlags{6} = SOPP; + + let TSFlags{7} = VOP1; + let TSFlags{8} = VOP2; + let TSFlags{9} = VOPC; + let TSFlags{10} = VOP3; + + let TSFlags{13} = VINTRP; let TSFlags{14} = SDWA; let TSFlags{15} = DPP; let TSFlags{16} = MUBUF; let TSFlags{17} = MTBUF; let TSFlags{18} = SMRD; - let TSFlags{19} = DS; - let TSFlags{20} = MIMG; + let TSFlags{19} = MIMG; + let TSFlags{20} = EXP; let TSFlags{21} = FLAT; - let TSFlags{22} = EXP; - let TSFlags{23} = WQM; - let TSFlags{24} = VGPRSpill; - let TSFlags{25} = SGPRSpill; - let TSFlags{26} = VOPAsmPrefer32Bit; - let TSFlags{27} = Gather4; - let TSFlags{28} = DisableWQM; - let TSFlags{29} = SOPKZext; - let TSFlags{30} = ScalarStore; - let TSFlags{31} = FixedSize; + let TSFlags{22} = DS; + + let TSFlags{23} = VGPRSpill; + let TSFlags{24} = SGPRSpill; + + let TSFlags{32} = VM_CNT; + let TSFlags{33} = EXP_CNT; + let TSFlags{34} = LGKM_CNT; + + let TSFlags{35} = WQM; + let TSFlags{36} = DisableWQM; + let TSFlags{37} = Gather4; + + let TSFlags{38} = SOPKZext; + let TSFlags{39} = ScalarStore; + let TSFlags{40} = FixedSize; + let TSFlags{41} = VOPAsmPrefer32Bit; let SchedRW = [Write32Bit];