Index: lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -870,7 +870,7 @@ if (!MI) continue; for (; DI != DE && - (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { + (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() <= Order; ++DI) { if ((*DI)->isInvalidated()) continue; MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap); Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -936,7 +936,12 @@ HandlePHINodesInSuccessorBlocks(I.getParent()); } - ++SDNodeOrder; + // Do not increment SDNodeOrder for debug intrinsics, because some parts + // of CodeGen rely on the node order (e.g. ScheduleDAGRRList). + // Debug nodes created use SDNodeOrder+1 to ensure they are placed after + // the previous instruction. + if (!isa(I)) + ++SDNodeOrder; CurInst = &I; @@ -4930,7 +4935,7 @@ if (isParameter && FINode) { // Byval parameter. We have a frame index at this point. SDV = DAG.getFrameIndexDbgValue(Variable, Expression, - FINode->getIndex(), 0, dl, SDNodeOrder); + FINode->getIndex(), 0, dl, SDNodeOrder+1); } else if (isa(Address)) { // Address is an argument, so try to emit its dbg value using // virtual register info from the FuncInfo.ValueMap. @@ -4939,7 +4944,7 @@ return nullptr; } else { SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), - true, 0, dl, SDNodeOrder); + true, 0, dl, SDNodeOrder+1); } DAG.AddDbgValue(SDV, N.getNode(), isParameter); } else { @@ -4955,7 +4960,7 @@ FuncInfo.StaticAllocaMap.find(AI); if (SI != FuncInfo.StaticAllocaMap.end()) { SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second, - 0, dl, SDNodeOrder); + 0, dl, SDNodeOrder+1); DAG.AddDbgValue(SDV, nullptr, false); return nullptr; } @@ -4967,6 +4972,7 @@ return nullptr; } case Intrinsic::dbg_value: { + const DbgValueInst &DI = cast(I); assert(DI.getVariable() && "Missing variable"); @@ -4980,7 +4986,7 @@ SDDbgValue *SDV; if (isa(V) || isa(V) || isa(V)) { SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl, - SDNodeOrder); + SDNodeOrder+1); DAG.AddDbgValue(SDV, nullptr, false); } else { // Do not use getValue() in here; we don't want to generate code at @@ -4992,13 +4998,13 @@ if (N.getNode()) { if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset, false, N)) { - SDV = getDbgValue(N, Variable, Expression, Offset, dl, SDNodeOrder); + SDV = getDbgValue(N, Variable, Expression, Offset, dl, SDNodeOrder+1); DAG.AddDbgValue(SDV, N.getNode(), false); } } else if (!V->use_empty() ) { // Do not call getValue(V) yet, as we don't want to generate code. // Remember it for later. - DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); + DanglingDebugInfo DDI(&DI, dl, SDNodeOrder+1); DanglingDebugInfoMap[V] = DDI; } else { // We may expand this to cover more cases. One case where we have no Index: test/CodeGen/X86/dbg_intrinsic_cfc.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/dbg_intrinsic_cfc.ll @@ -0,0 +1,100 @@ +; Check that debug intrinsics do not affect code generation. + +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s + +define i64 @simulate(<2 x i32> %a) { +entry: + %rand = tail call i64 @lrand48() + br label %body + +body: ; preds = %body, %entry + %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ] + %add = add <2 x i32> %0, %a + %rand1 = tail call i64 @lrand48() #3 + %cmp = icmp eq i64 %rand1, 0 + br i1 %cmp, label %end, label %body + +end: ; preds = %body + %c = bitcast <2 x i32> %add to i64 + %res = add i64 %rand, %c + ret i64 %res +} + +; CHECK: simulate: +; CHECK: movdqa %xmm0, 16(%rsp) +; CHECK: pxor %xmm0, %xmm0 +; CHECK: movdqa %xmm0, (%rsp) +; CHECK: callq lrand48 +; CHECK: movq %rax, %rbx + + +define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr { +entry: + %rand = tail call i64 @lrand48() #3 + tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8 + br label %body + +body: ; preds = %body, %entry + %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ] + %add = add <2 x i32> %0, %a + %rand1 = tail call i64 @lrand48() #3 + %cmp = icmp eq i64 %rand1, 0 + br i1 %cmp, label %end, label %body + +end: ; preds = %body + %c = bitcast <2 x i32> %add to i64 + %res = add i64 %rand, %c + ret i64 %res +} + +; CHECK: simulateWithDebugIntrinsic: +; CHECK: movdqa %xmm0, 16(%rsp) +; CHECK: pxor %xmm0, %xmm0 +; CHECK: movdqa %xmm0, (%rsp) +; CHECK: callq lrand48 +; CHECK: movq %rax, %rbx + +define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr { +entry: + %rand = tail call i64 @lrand48() #3 + tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8 + br label %body + +body: ; preds = %body, %entry + %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ] + %add = add <2 x i32> %0, %a + %rand1 = tail call i64 @lrand48() #3 + %cmp = icmp eq i64 %rand1, 0 + br i1 %cmp, label %end, label %body + +end: ; preds = %body + %c = bitcast <2 x i32> %add to i64 + %res = add i64 %rand, %c + ret i64 %res +} + +; CHECK: simulateWithDbgDeclare: +; CHECK: movdqa %xmm0, 16(%rsp) +; CHECK: pxor %xmm0, %xmm0 +; CHECK: movdqa %xmm0, (%rsp) +; CHECK: callq lrand48 +; CHECK: movq %rax, %rbx + + + +declare i64 @lrand48() + +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!3, !4} + +!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug) +!2 = !DIFile(filename: "test.ll", directory: ".") +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1) +!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69) +!7 = !DIExpression() +!8 = !DILocation(line: 132, column: 2, scope: !5) Index: test/DebugInfo/X86/dbg-value-dag-combine.ll =================================================================== --- test/DebugInfo/X86/dbg-value-dag-combine.ll +++ test/DebugInfo/X86/dbg-value-dag-combine.ll @@ -6,8 +6,8 @@ ; There should be a DEBUG_VALUE for each call to llvm.dbg.value ; CHECK: ##DEBUG_VALUE: __OpenCL_test_kernel:ip <- -; CHECK: ##DEBUG_VALUE: xxx <- 0 ; CHECK: ##DEBUG_VALUE: gid <- %E{{..$}} +; CHECK: ##DEBUG_VALUE: xxx <- 0 ; CHECK: ##DEBUG_VALUE: idx <- %E{{..$}} ; CHECK-NOT: ##DEBUG_VALUE: Index: test/DebugInfo/X86/pieces-4.ll =================================================================== --- test/DebugInfo/X86/pieces-4.ll +++ test/DebugInfo/X86/pieces-4.ll @@ -15,8 +15,8 @@ ; CHECK-LABEL: bitpiece_spill: # @bitpiece_spill ; CHECK: callq g ; CHECK: movl %eax, [[offs:[0-9]+]](%rsp) # 4-byte Spill -; CHECK: #DEBUG_VALUE: bitpiece_spill:o [bit_piece offset=32 size=32] <- 0 ; CHECK: #DEBUG_VALUE: bitpiece_spill:o [bit_piece offset=0 size=32] <- [%RSP+[[offs]]] +; CHECK: #DEBUG_VALUE: bitpiece_spill:o [bit_piece offset=32 size=32] <- 0 ; CHECK: #APP ; CHECK: #NO_APP ; CHECK: movl [[offs]](%rsp), %eax # 4-byte Reload