Index: lib/Target/Lanai/LanaiISelDAGToDAG.cpp =================================================================== --- lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -282,9 +282,27 @@ return; } - // Instruction Selection not handled by the auto-generated - // tablegen selection should be handled here. + // Instruction Selection not handled by the auto-generated tablegen selection + // should be handled here. switch (Opcode) { + case ISD::Constant: { + ConstantSDNode *ConstNode = cast(Node); + // Materialize zero constants as copies from R0. This allows the coalescer + // to propagate these into other instructions. + if (ConstNode->isNullValue()) { + SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), + Lanai::R0, MVT::i32); + return ReplaceNode(Node, New.getNode()); + } + // Materialize all ones constants as copies from R1. This allows the + // coalescer to propagate these into other instructions. + if (ConstNode->isAllOnesValue()) { + SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), + Lanai::R1, MVT::i32); + return ReplaceNode(Node, New.getNode()); + } + break; + } case ISD::FrameIndex: selectFrameIndex(Node); return; Index: lib/Target/Lanai/LanaiInstrInfo.td =================================================================== --- lib/Target/Lanai/LanaiInstrInfo.td +++ lib/Target/Lanai/LanaiInstrInfo.td @@ -831,11 +831,6 @@ // Non-Instruction Patterns //===----------------------------------------------------------------------===// -// i32 0 and R0 can be used interchangeably. -def : Pat<(i32 0), (i32 R0)>; -// i32 -1 and R1 can be used interchangeably. -def : Pat<(i32 -1), (i32 R1)>; - // unsigned 16-bit immediate def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>; Index: test/CodeGen/Lanai/constant_multiply.ll =================================================================== --- test/CodeGen/Lanai/constant_multiply.ll +++ test/CodeGen/Lanai/constant_multiply.ll @@ -81,18 +81,18 @@ } ; CHECK-LABEL: fm9: -; CHECK: sh %r6, 0x3, %r{{[0-9]+}} -; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}} -; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +; CHECK: sub %r0, %r6, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r9 +; CHECK: sub %r{{[0-9]+}}, %r9, %rv define i32 @fm9(i32 inreg %a) #0 { %1 = mul nsw i32 %a, -9 ret i32 %1 } ; CHECK-LABEL: fm10: -; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sh %r6, 0x1, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv define i32 @fm10(i32 inreg %a) #0 { %1 = mul nsw i32 %a, -10