Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -27617,6 +27617,26 @@
   SDLoc DL(N);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
+  bool FValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
+  //Check if the first operand is all zeros.
+  if (FValIsAllZeros &&
+      // Check if the selector will be produced by CMPP*/PCMP*.
+      Cond.getOpcode() == ISD::SETCC &&
+      N->getOpcode() == ISD::VSELECT) {
+      ISD::CondCode CC = cast<CondCodeSDNode>(Cond->getOperand(2))->get();
+      // Check if the compare instruction uses SETEQ with all zeros. 
+      if (CC == ISD::SETEQ) {
+        SDValue CC = Cond.getOperand(2);
+        ISD::CondCode NewCC = ISD::getSetCCInverse(
+                                   cast<CondCodeSDNode>(CC)->get(),
+                                   Cond.getOperand(0).getValueType().isInteger());
+        SDValue CondNew = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), 
+                                       Cond.getOperand(1), NewCC);
+        return DAG.getNode(ISD::VSELECT, DL, VT, CondNew, 
+                           N->getOperand(2), N->getOperand(1));
+      }
+  }
+
   if (N->getOpcode() != ISD::VSELECT)
     return SDValue();
 
@@ -27631,7 +27651,7 @@
     return SDValue();
 
   bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
-  bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
+  FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
 
   // Try to invert the condition if true value is not all 1s and false value is
   // not all 0s.
Index: test/CodeGen/X86/avx512-vec-cmp.ll
===================================================================
--- test/CodeGen/X86/avx512-vec-cmp.ll
+++ test/CodeGen/X86/avx512-vec-cmp.ll
@@ -658,10 +658,9 @@
 define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
 ; CHECK-LABEL: test14:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpsubd %zmm1, %zmm0, %zmm1
-; CHECK-NEXT:    vpcmpled %zmm0, %zmm1, %k0
-; CHECK-NEXT:    knotw %k0, %k1
-; CHECK-NEXT:    vmovdqa32 %zmm1, %zmm0 {%k1} {z}
+; CHECK-NEXT:    vpsubd %zmm1, %zmm0, %zmm2
+; CHECK-NEXT:    vpcmpgtd    %zmm0, %zmm2, %k1
+; CHECK-NEXT:    vpsubd  %zmm1, %zmm0, %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %sub_r = sub <16 x i32> %a, %b
   %cmp.i2.i = icmp sgt <16 x i32> %sub_r, %a
@@ -674,10 +673,9 @@
 define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
 ; CHECK-LABEL: test15:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpsubq %zmm1, %zmm0, %zmm1
-; CHECK-NEXT:    vpcmpleq %zmm0, %zmm1, %k0
-; CHECK-NEXT:    knotw %k0, %k1
-; CHECK-NEXT:    vmovdqa64 %zmm1, %zmm0 {%k1} {z}
+; CHECK-NEXT:    vpsubq  %zmm1, %zmm0, %zmm2  
+; CHECK-NEXT:    vpcmpgtq    %zmm0, %zmm2, %k1
+; CHECK-NEXT:    vpsubq  %zmm1, %zmm0, %zmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
   %sub_r = sub <8 x i64> %a, %b
   %cmp.i2.i = icmp sgt <8 x i64> %sub_r, %a