Index: lib/Target/AMDGPU/SIRegisterInfo.td
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.td
+++ lib/Target/AMDGPU/SIRegisterInfo.td
@@ -257,14 +257,14 @@
 // Subset of SReg_32 without M0 for SMRD instructions and alike.
 // See comments in SIInstructions.td for more info.
 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
-  (add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
+  (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
    TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)> {
   let AllocationPriority = 1;
 }
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
-  (add SReg_32_XM0, M0_CLASS)> {
+  (add SReg_32_XM0, EXEC_LO, EXEC_HI, M0_CLASS)> {
   let AllocationPriority = 1;
   let isAllocatable = 0;
 }
Index: test/CodeGen/AMDGPU/read_register.ll
===================================================================
--- test/CodeGen/AMDGPU/read_register.ll
+++ test/CodeGen/AMDGPU/read_register.ll
@@ -55,7 +55,8 @@
 }
 
 ; CHECK-LABEL: {{^}}test_read_exec_lo:
-; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
+; CHECK: s_mov_b32 [[SCOPY:s[0-9]+]], exec_lo
+; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], [[SCOPY]]
 ; CHECK: buffer_store_dword [[COPY]]
 define void @test_read_exec_lo(i32 addrspace(1)* %out) #0 {
   %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
@@ -64,7 +65,8 @@
 }
 
 ; CHECK-LABEL: {{^}}test_read_exec_hi:
-; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
+; CHECK: s_mov_b32 [[SCOPY:s[0-9]+]], exec_hi
+; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], [[SCOPY]]
 ; CHECK: buffer_store_dword [[COPY]]
 define void @test_read_exec_hi(i32 addrspace(1)* %out) #0 {
   %exec_hi = call i32 @llvm.read_register.i32(metadata !6)