Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -476,7 +476,7 @@
       = MF->getMachineMemOperand(PInfo, MMO->getFlags(),
                                  EltSize, MinAlign(Align, EltSize * i));
 
-    BuildMI(*MBB, MI, DL, Desc)
+    auto MIB = BuildMI(*MBB, MI, DL, Desc)
       .addReg(SubReg, getDefRegState(!IsStore))
       .addReg(ScratchRsrcReg)
       .addReg(SOffset, SOffsetRegState)
@@ -484,8 +484,10 @@
       .addImm(0) // glc
       .addImm(0) // slc
       .addImm(0) // tfe
-      .addMemOperand(NewMMO)
-      .addReg(ValueReg, RegState::Implicit | SrcDstRegState);
+      .addMemOperand(NewMMO);
+
+    if (NumSubRegs > 1)
+      MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
   }
 
   if (RanOutOfSGPRs) {
@@ -660,12 +662,15 @@
           .addReg(MFI->getScratchWaveOffsetReg());
       }
 
-      BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), SubReg)
+      auto MIB =
+        BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), SubReg)
         .addReg(MFI->getScratchRSrcReg()) // sbase
         .addReg(OffsetReg)                // soff
         .addImm(0)                        // glc
-        .addMemOperand(MMO)
-        .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
+        .addMemOperand(MMO);
+
+      if (NumSubRegs > 1)
+        MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
 
       continue;
     }