Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -507,13 +507,6 @@
 
     if (SpillToSMEM) {
       int64_t FrOffset = FrameInfo.getObjectOffset(Index);
-      unsigned Size = FrameInfo.getObjectSize(Index);
-      unsigned Align = FrameInfo.getObjectAlignment(Index);
-      MachinePointerInfo PtrInfo
-        = MachinePointerInfo::getFixedStack(*MF, Index);
-      MachineMemOperand *MMO
-        = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
-                                   Size, Align);
 
       unsigned OffsetReg = AMDGPU::M0;
       // Add i * 4 wave offset.
@@ -536,7 +529,7 @@
         .addReg(MFI->getScratchRSrcReg())        // sbase
         .addReg(OffsetReg)                       // soff
         .addImm(0)                               // glc
-        .addMemOperand(MMO);
+        .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
 
       continue;
     }
@@ -574,20 +567,13 @@
         Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
       }
 
-      unsigned Size = FrameInfo.getObjectSize(Index);
-      unsigned Align = FrameInfo.getObjectAlignment(Index);
-      MachinePointerInfo PtrInfo
-        = MachinePointerInfo::getFixedStack(*MF, Index);
-      MachineMemOperand *MMO
-        = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
-                                   Size, Align);
       BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
         .addReg(TmpReg, RegState::Kill)         // src
         .addFrameIndex(Index)                   // vaddr
         .addReg(MFI->getScratchRSrcReg())       // srrsrc
         .addReg(MFI->getScratchWaveOffsetReg()) // soffset
         .addImm(i * 4)                          // offset
-        .addMemOperand(MMO);
+        .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
     }
   }
 
@@ -620,14 +606,6 @@
       SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));
 
     if (SpillToSMEM) {
-      unsigned Size = FrameInfo.getObjectSize(Index);
-      unsigned Align = FrameInfo.getObjectAlignment(Index);
-      MachinePointerInfo PtrInfo
-        = MachinePointerInfo::getFixedStack(*MF, Index);
-      MachineMemOperand *MMO
-        = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
-                                   Size, Align);
-
       unsigned OffsetReg = AMDGPU::M0;
 
       // Add i * 4 offset
@@ -645,8 +623,8 @@
         .addReg(MFI->getScratchRSrcReg()) // sbase
         .addReg(OffsetReg)                // soff
         .addImm(0)                        // glc
-        .addMemOperand(MMO)
-        .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
+        .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine)
+        .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
 
       continue;
     }
@@ -666,23 +644,15 @@
       // FIXME: We should use S_LOAD_DWORD here for VI.
 
       unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-      unsigned Align = FrameInfo.getObjectAlignment(Index);
-      unsigned Size = FrameInfo.getObjectSize(Index);
-
-      MachinePointerInfo PtrInfo
-        = MachinePointerInfo::getFixedStack(*MF, Index);
-
-      MachineMemOperand *MMO = MF->getMachineMemOperand(
-        PtrInfo, MachineMemOperand::MOLoad, Size, Align);
 
       BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
         .addFrameIndex(Index)                   // vaddr
         .addReg(MFI->getScratchRSrcReg())       // srsrc
         .addReg(MFI->getScratchWaveOffsetReg()) // soffset
         .addImm(i * 4)                          // offset
-        .addMemOperand(MMO);
-      BuildMI(*MBB, MI, DL,
-              TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
+        .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
+
+      BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
         .addReg(TmpReg, RegState::Kill)
         .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
     }