Index: include/llvm/MC/MCSubtargetInfo.h
===================================================================
--- include/llvm/MC/MCSubtargetInfo.h
+++ include/llvm/MC/MCSubtargetInfo.h
@@ -45,6 +45,9 @@
   unsigned NumProcs;                   // Number of processors
   uint64_t FeatureBits;                // Feature bits for current CPU + FS
 
+  bool UseIntegratedInlineAs; // Should we use the integrated assembler for
+                              // inline assembly on this subtarget.
+
 public:
   void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
                            const SubtargetFeatureKV *PF,
@@ -68,6 +71,15 @@
     return FeatureBits;
   }
 
+  /// useIntegratedInlineAs - Return true if the inline assembly should be
+  /// parsed.
+  bool useIntegratedInlineAs() const { return UseIntegratedInlineAs; }
+
+  /// isIntegratedAsDefault - Is the integrated assembler enabled by default
+  /// The integrated assembler should be enabled by default when failing to
+  /// parse a valid piece of assembly (inline or otherwise) is considered a bug.
+  bool isIntegratedAsDefault(StringRef TT) const;
+
   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
   /// feature string). Recompute feature bits and scheduling model.
   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
Index: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
===================================================================
--- lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
+++ lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
@@ -79,10 +79,12 @@
   if (isNullTerminated)
     Str = Str.substr(0, Str.size()-1);
 
-  // If the output streamer is actually a .s file, just emit the blob textually.
+  // If the output streamer does not have mature MC support or the integrated
+  // assembler has been disabled, just emit the blob textually.
+  // Otherwise parse the asm and emit it via MC support.
   // This is useful in case the asm parser doesn't handle something but the
   // system assembler does.
-  if (OutStreamer.hasRawTextSupport()) {
+  if (!TM.getSubtarget<MCSubtargetInfo>().useIntegratedInlineAs()) {
     OutStreamer.EmitRawText(Str);
     emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), 0);
     return;
Index: lib/MC/MCSubtargetInfo.cpp
===================================================================
--- lib/MC/MCSubtargetInfo.cpp
+++ lib/MC/MCSubtargetInfo.cpp
@@ -13,10 +13,15 @@
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/CommandLine.h"
 #include <algorithm>
 
 using namespace llvm;
 
+static cl::opt<bool>                                                              
+NoIntegratedInlineAs("no-integrated-inline-as", cl::Hidden,             
+                     cl::desc("Disable integrated assembly of inline asm"));
+
 MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
 
 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
@@ -64,6 +69,10 @@
   NumFeatures = NF;
   NumProcs = NP;
 
+  UseIntegratedInlineAs = isIntegratedAsDefault(TT);
+  if (NoIntegratedInlineAs)
+    UseIntegratedInlineAs = false;
+
   InitMCProcessorInfo(CPU, FS);
 }
 
@@ -119,3 +128,18 @@
   InstrItins =
     InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
 }
+
+bool MCSubtargetInfo::isIntegratedAsDefault(StringRef TT) const {
+  Triple Trip(TT);
+
+  // This should be kept in sync with clang
+  if (Trip.getArch() == llvm::Triple::aarch64 ||
+      Trip.getArch() == llvm::Triple::arm ||
+      Trip.getArch() == llvm::Triple::x86 ||
+      Trip.getArch() == llvm::Triple::x86_64 ||
+      Trip.getArch() == llvm::Triple::thumb)
+    return true;
+
+  return false;
+}
+
Index: test/CodeGen/AArch64/inline-asm-constraints.ll
===================================================================
--- test/CodeGen/AArch64/inline-asm-constraints.ll
+++ test/CodeGen/AArch64/inline-asm-constraints.ll
@@ -1,4 +1,4 @@
-;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -no-integrated-inline-as < %s | FileCheck %s
 
 define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
 ; CHECK-LABEL: test_inline_constraint_r:
Index: test/CodeGen/AArch64/inline-asm-modifiers.ll
===================================================================
--- test/CodeGen/AArch64/inline-asm-modifiers.ll
+++ test/CodeGen/AArch64/inline-asm-modifiers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -no-integrated-inline-as < %s | FileCheck %s
 
 @var_simple = hidden global i32 0
 @var_got = global i32 0
Index: test/CodeGen/ARM/2009-04-06-AsmModifier.ll
===================================================================
--- test/CodeGen/ARM/2009-04-06-AsmModifier.ll
+++ test/CodeGen/ARM/2009-04-06-AsmModifier.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm | grep "swi 107"
+; RUN: llc < %s -march=arm -no-integrated-inline-as | grep "swi 107"
 
 define i32 @_swilseek(i32) nounwind {
 entry:
Index: test/CodeGen/ARM/arm-modifier.ll
===================================================================
--- test/CodeGen/ARM/arm-modifier.ll
+++ test/CodeGen/ARM/arm-modifier.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-inline-as | FileCheck %s
 
 define i32 @foo(float %scale, float %scale2) nounwind {
 entry:
Index: test/CodeGen/ARM/crash-O0.ll
===================================================================
--- test/CodeGen/ARM/crash-O0.ll
+++ test/CodeGen/ARM/crash-O0.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim -no-integrated-inline-as
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
 target triple = "armv6-apple-darwin10"
 
Index: test/CodeGen/ARM/inlineasm-64bit.ll
===================================================================
--- test/CodeGen/ARM/inlineasm-64bit.ll
+++ test/CodeGen/ARM/inlineasm-64bit.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O3  -mtriple=arm-linux-gnueabi | FileCheck %s
-; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc < %s -O3  -mtriple=arm-linux-gnueabi -no-integrated-inline-as | FileCheck %s
+; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-inline-as < %s | FileCheck %s
 ; check if regs are passing correctly
 define void @i64_write(i64* %p, i64 %val) nounwind {
 ; CHECK-LABEL: i64_write:
Index: test/CodeGen/ARM/inlineasm-imm-arm.ll
===================================================================
--- test/CodeGen/ARM/inlineasm-imm-arm.ll
+++ test/CodeGen/ARM/inlineasm-imm-arm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm -no-integrated-inline-as
 
 ; Test ARM-mode "I" constraint, for any Data Processing immediate.
 define i32 @testI(i32 %x) {
Index: test/CodeGen/ARM/inlineasm3.ll
===================================================================
--- test/CodeGen/ARM/inlineasm3.ll
+++ test/CodeGen/ARM/inlineasm3.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 | FileCheck %s
+; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-inline-as | FileCheck %s
 
 ; Radar 7449043
 %struct.int32x4_t = type { <4 x i32> }
Index: test/CodeGen/ARM/mult-alt-generic-arm.ll
===================================================================
--- test/CodeGen/ARM/mult-alt-generic-arm.ll
+++ test/CodeGen/ARM/mult-alt-generic-arm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm -no-integrated-inline-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
 target triple = "arm"
Index: test/CodeGen/ARM/subreg-remat.ll
===================================================================
--- test/CodeGen/ARM/subreg-remat.ll
+++ test/CodeGen/ARM/subreg-remat.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-inline-as | FileCheck %s
 target triple = "thumbv7-apple-ios"
 ; <rdar://problem/10032939>
 ;
Index: test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
===================================================================
--- test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
+++ test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -no-integrated-inline-as < %s
 ; XFAIL: sparc-sun-solaris2
 ; PR1308
 ; PR1557
Index: test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
===================================================================
--- test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
+++ test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -no-integrated-inline-as < %s
 
 ; Test that we can have an "X" output constraint.
 
Index: test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
===================================================================
--- test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
+++ test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -no-integrated-inline-as < %s
 
         %struct..0anon = type { [100 x i32] }
 
Index: test/CodeGen/Generic/2008-02-20-MatchingMem.ll
===================================================================
--- test/CodeGen/Generic/2008-02-20-MatchingMem.ll
+++ test/CodeGen/Generic/2008-02-20-MatchingMem.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -no-integrated-inline-as < %s
 ; PR1133
 ; XFAIL: hexagon
 define void @test(i32* %X) nounwind  {
Index: test/CodeGen/Generic/asm-large-immediate.ll
===================================================================
--- test/CodeGen/Generic/asm-large-immediate.ll
+++ test/CodeGen/Generic/asm-large-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
 
 define void @test() {
 entry:
Index: test/CodeGen/Generic/inline-asm-mem-clobber.ll
===================================================================
--- test/CodeGen/Generic/inline-asm-mem-clobber.ll
+++ test/CodeGen/Generic/inline-asm-mem-clobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O2 < %s | FileCheck %s
+; RUN: llc -O2 -no-integrated-inline-as < %s | FileCheck %s
 
 @G = common global i32 0, align 4
 
Index: test/CodeGen/Generic/inline-asm-special-strings.ll
===================================================================
--- test/CodeGen/Generic/inline-asm-special-strings.ll
+++ test/CodeGen/Generic/inline-asm-special-strings.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | grep "foo 0 0"
+; RUN: llc -no-integrated-inline-as < %s | grep "foo 0 0"
 
 define void @bar() nounwind {
 	tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind
Index: test/CodeGen/Generic/mature-mc-support.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Generic/mature-mc-support.ll
@@ -0,0 +1,16 @@
+; Test that inline assembly is parsed by the MC layer when MC support is mature.
+
+; RUN: not llc -march=aarch64 < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=aarch64 -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=arm < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=arm -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=thumb < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=thumb -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86 < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86 -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86-64 < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86-64 -filetype=obj < %s 2>&1 | FileCheck %s
+
+module asm "	.this_directive_is_very_unlikely_to_exist"
+
+; CHECK: LLVM ERROR: Error parsing inline asm
Index: test/CodeGen/Thumb/inlineasm-imm-thumb.ll
===================================================================
--- test/CodeGen/Thumb/inlineasm-imm-thumb.ll
+++ test/CodeGen/Thumb/inlineasm-imm-thumb.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=thumb
+; RUN: llc < %s -march=thumb -no-integrated-inline-as
 
 ; Test Thumb-mode "I" constraint, for ADD immediate.
 define i32 @testI(i32 %x) {
Index: test/CodeGen/X86/2006-07-20-InlineAsm.ll
===================================================================
--- test/CodeGen/X86/2006-07-20-InlineAsm.ll
+++ test/CodeGen/X86/2006-07-20-InlineAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-inline-as
 ; PR833
 
 @G = weak global i32 0		; <i32*> [#uses=3]
Index: test/CodeGen/X86/2006-07-31-SingleRegClass.ll
===================================================================
--- test/CodeGen/X86/2006-07-31-SingleRegClass.ll
+++ test/CodeGen/X86/2006-07-31-SingleRegClass.ll
@@ -1,5 +1,5 @@
 ; PR850
-; RUN: llc < %s -march=x86 -x86-asm-syntax=att | FileCheck %s
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att -no-integrated-inline-as | FileCheck %s
 
 ; CHECK: {{movl 4[(]%eax[)],%ebp}}
 ; CHECK: {{movl 0[(]%eax[)], %ebx}}
Index: test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
===================================================================
--- test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
+++ test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep "mov %gs:72, %eax"
+; RUN: llc < %s -march=x86 -no-integrated-inline-as | grep "mov %gs:72, %eax"
 target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9"
 
Index: test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
===================================================================
--- test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
+++ test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=yonah -march=x86 | FileCheck %s
+; RUN: llc < %s -mcpu=yonah -march=x86 -no-integrated-inline-as | FileCheck %s
 
 target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9"
Index: test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
===================================================================
--- test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
+++ test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -no-integrated-inline-as < %s
 ; PR1748
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
Index: test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
===================================================================
--- test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
+++ test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc -no-integrated-inline-as < %s -mtriple=x86_64-unknown-linux-gnu
 ; PR1767
 
 define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {
Index: test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
===================================================================
--- test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
+++ test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -relocation-model=static | FileCheck %s
+; RUN: llc < %s -relocation-model=static -no-integrated-inline-as | FileCheck %s
 ; PR1761
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-pc-linux"
Index: test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
===================================================================
--- test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
+++ test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
 ; PR2078
 ; The clobber list says that "ax" is clobbered.  Make sure that eax isn't 
 ; allocated to the input/output register.
Index: test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
===================================================================
--- test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
+++ test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-inline-as
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
 target triple = "i386-pc-linux-gnu"
Index: test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
===================================================================
--- test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
+++ test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
 ; rdar://5720231
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin8"
Index: test/CodeGen/X86/2008-09-18-inline-asm-2.ll
===================================================================
--- test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=basic      | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=greedy     | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-inline-as | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-inline-as      | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-inline-as     | FileCheck %s
 
 ; The 1st, 2nd, 3rd and 5th registers must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
Index: test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
===================================================================
--- test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
+++ test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86 -no-integrated-inline-as
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as
 
 define void @test(i64 %x) nounwind {
 entry:
Index: test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
===================================================================
--- test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
+++ test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86 -no-integrated-inline-as
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as
 
 ; from gcc.c-torture/compile/920520-1.c
 
Index: test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
===================================================================
--- test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
+++ test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -no-integrated-inline-as | FileCheck %s
 
 ; ModuleID = 'shant.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
Index: test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
===================================================================
--- test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
+++ test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin
+; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-inline-as
 ; rdar://6781755
 ; PR3934
 
Index: test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
===================================================================
--- test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
+++ test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -relocation-model=static | FileCheck %s
+; RUN: llc < %s -relocation-model=static -no-integrated-inline-as | FileCheck %s
 ; PR4152
 
 ; CHECK: {{1: ._pv_cpu_ops[+]8}}
Index: test/CodeGen/X86/2009-09-19-earlyclobber.ll
===================================================================
--- test/CodeGen/X86/2009-09-19-earlyclobber.ll
+++ test/CodeGen/X86/2009-09-19-earlyclobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
 ; ModuleID = '4964.c'
 ; PR 4964
 ; Registers other than RAX, RCX are OK, but they must be different.
Index: test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
===================================================================
--- test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
+++ test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-inline-as | FileCheck %s
 ; pr5391
 
 define void @t() nounwind ssp {
Index: test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
===================================================================
--- test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
+++ test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s
+; RUN: llc < %s -O0 -regalloc=fast -no-integrated-inline-as | FileCheck %s
 ; PR6520
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
Index: test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
===================================================================
--- test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
+++ test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc -regalloc=fast -optimize-regalloc=0 < %s | FileCheck %s
+; RUN: llc -regalloc=fast -optimize-regalloc=0 -no-integrated-inline-as < %s | FileCheck %s
 ; PR7382
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
Index: test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
===================================================================
--- test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
+++ test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32
+; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 -no-integrated-inline-as
 
 %struct.__SEH2Frame = type {}
 
Index: test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
===================================================================
--- test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
+++ test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -O0 | FileCheck %s
+; RUN: llc < %s -march=x86 -O0 -no-integrated-inline-as | FileCheck %s
 ; PR7509
 target triple = "i386-apple-darwin10"
 %asmtype = type { i32, i8*, i32, i32 }
Index: test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
===================================================================
--- test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
+++ test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -no-integrated-inline-as | FileCheck %s
 ; Any register is OK for %0, but it must be a register, not memory.
 
 define i32 @foo() nounwind ssp {
Index: test/CodeGen/X86/2010-07-02-asm-alignstack.ll
===================================================================
--- test/CodeGen/X86/2010-07-02-asm-alignstack.ll
+++ test/CodeGen/X86/2010-07-02-asm-alignstack.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -no-integrated-inline-as | FileCheck %s
 
 define void @foo() nounwind ssp {
 entry:
Index: test/CodeGen/X86/2010-07-06-asm-RIP.ll
===================================================================
--- test/CodeGen/X86/2010-07-06-asm-RIP.ll
+++ test/CodeGen/X86/2010-07-06-asm-RIP.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-inline-as | FileCheck %s
 ; PR 4752
 
 @n = global i32 0                                 ; <i32*> [#uses=2]
Index: test/CodeGen/X86/2010-07-13-indirectXconstraint.ll
===================================================================
--- test/CodeGen/X86/2010-07-13-indirectXconstraint.ll
+++ test/CodeGen/X86/2010-07-13-indirectXconstraint.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-inline-as | FileCheck %s
 ; PR 7528
 ; formerly crashed
 
Index: test/CodeGen/X86/2011-10-11-SpillDead.ll
===================================================================
--- test/CodeGen/X86/2011-10-11-SpillDead.ll
+++ test/CodeGen/X86/2011-10-11-SpillDead.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-regalloc
+; RUN: llc < %s -verify-regalloc -no-integrated-inline-as
 ; PR11125
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.7"
Index: test/CodeGen/X86/asm-block-labels.ll
===================================================================
--- test/CodeGen/X86/asm-block-labels.ll
+++ test/CodeGen/X86/asm-block-labels.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -std-compile-opts | llc
+; RUN: opt < %s -std-compile-opts | llc -no-integrated-inline-as
 ; ModuleID = 'block12.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin8"
Index: test/CodeGen/X86/asm-global-imm.ll
===================================================================
--- test/CodeGen/X86/asm-global-imm.ll
+++ test/CodeGen/X86/asm-global-imm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s
+; RUN: llc < %s -march=x86 -relocation-model=static -no-integrated-inline-as | FileCheck %s
 ; PR882
 
 target datalayout = "e-p:32:32"
Index: test/CodeGen/X86/cas.ll
===================================================================
--- test/CodeGen/X86/cas.ll
+++ test/CodeGen/X86/cas.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - -no-integrated-inline-as | FileCheck %s
 
 ; C code this came from
 ;bool cas(float volatile *p, float *expected, float desired) {
Index: test/CodeGen/X86/fast-isel.ll
===================================================================
--- test/CodeGen/X86/fast-isel.ll
+++ test/CodeGen/X86/fast-isel.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2
-; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-inline-as
+; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-inline-as
 
 ; This tests very minimal fast-isel functionality.
 
Index: test/CodeGen/X86/fold-xmm-zero.ll
===================================================================
--- test/CodeGen/X86/fold-xmm-zero.ll
+++ test/CodeGen/X86/fold-xmm-zero.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 -no-integrated-inline-as | FileCheck %s
 
 ; Simple test to make sure folding for special constants (like float zero)
 ; isn't completely broken.
Index: test/CodeGen/X86/inline-asm-flag-clobber.ll
===================================================================
--- test/CodeGen/X86/inline-asm-flag-clobber.ll
+++ test/CodeGen/X86/inline-asm-flag-clobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86-64 < %s | FileCheck %s
+; RUN: llc -march=x86-64 -no-integrated-inline-as < %s | FileCheck %s
 ; PR3701
 
 define i64 @t(i64* %arg) nounwind {
Index: test/CodeGen/X86/inline-asm-fpstack.ll
===================================================================
--- test/CodeGen/X86/inline-asm-fpstack.ll
+++ test/CodeGen/X86/inline-asm-fpstack.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -no-integrated-inline-as | FileCheck %s
 
 ; There should be no stack manipulations between the inline asm and ret.
 ; CHECK: test1
Index: test/CodeGen/X86/inline-asm-h.ll
===================================================================
--- test/CodeGen/X86/inline-asm-h.ll
+++ test/CodeGen/X86/inline-asm-h.ll
@@ -9,4 +9,4 @@
 }
 
 ; CHECK: zed
-; CHECK: movq %mm2,foobar+8(%rip)
+; CHECK: movq %mm2, foobar+8(%rip)
Index: test/CodeGen/X86/inline-asm-modifier-n.ll
===================================================================
--- test/CodeGen/X86/inline-asm-modifier-n.ll
+++ test/CodeGen/X86/inline-asm-modifier-n.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep " 37"
+; RUN: llc < %s -march=x86 -no-integrated-inline-as | grep " 37"
 ; rdar://7008959
 
 define void @bork() nounwind {
Index: test/CodeGen/X86/inline-asm-mrv.ll
===================================================================
--- test/CodeGen/X86/inline-asm-mrv.ll
+++ test/CodeGen/X86/inline-asm-mrv.ll
@@ -1,8 +1,8 @@
 ; PR2094
-; RUN: llc < %s -march=x86-64 | grep movslq
-; RUN: llc < %s -march=x86-64 | grep addps
-; RUN: llc < %s -march=x86-64 | grep paddd
-; RUN: llc < %s -march=x86-64 | not grep movq
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | grep movslq
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | grep addps
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | grep paddd
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | not grep movq
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin8"
Index: test/CodeGen/X86/inline-asm-q-regs.ll
===================================================================
--- test/CodeGen/X86/inline-asm-q-regs.ll
+++ test/CodeGen/X86/inline-asm-q-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=+avx
+; RUN: llc < %s -march=x86-64 -mattr=+avx -no-integrated-inline-as
 ; rdar://7066579
 
 	%0 = type { i64, i64, i64, i64, i64 }		; type %0
Index: test/CodeGen/X86/inline-asm-stack-realign3.ll
===================================================================
--- test/CodeGen/X86/inline-asm-stack-realign3.ll
+++ test/CodeGen/X86/inline-asm-stack-realign3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86 < %s | FileCheck %s
+; RUN: llc -march=x86 -no-integrated-inline-as < %s | FileCheck %s
 
 declare void @bar(i32* %junk)
 
Index: test/CodeGen/X86/inline-asm-tied.ll
===================================================================
--- test/CodeGen/X86/inline-asm-tied.ll
+++ test/CodeGen/X86/inline-asm-tied.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic -no-integrated-inline-as | FileCheck %s
 ; rdar://6992609
 
 ; CHECK: movl [[EDX:%e..]], 4(%esp)
Index: test/CodeGen/X86/inline-asm-x-scalar.ll
===================================================================
--- test/CodeGen/X86/inline-asm-x-scalar.ll
+++ test/CodeGen/X86/inline-asm-x-scalar.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah -no-integrated-inline-as
 
 define void @test1() {
         tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000)
Index: test/CodeGen/X86/inline-asm.ll
===================================================================
--- test/CodeGen/X86/inline-asm.ll
+++ test/CodeGen/X86/inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-inline-as
 
 define i32 @test1() nounwind {
 	; Dest is AX, dest type = i32.
Index: test/CodeGen/X86/ms-inline-asm.ll
===================================================================
--- test/CodeGen/X86/ms-inline-asm.ll
+++ test/CodeGen/X86/ms-inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=core2 -no-integrated-inline-as | FileCheck %s
 
 define i32 @t1() nounwind {
 entry:
Index: test/CodeGen/X86/mult-alt-generic-i686.ll
===================================================================
--- test/CodeGen/X86/mult-alt-generic-i686.ll
+++ test/CodeGen/X86/mult-alt-generic-i686.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-inline-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i686"
Index: test/CodeGen/X86/mult-alt-generic-x86_64.ll
===================================================================
--- test/CodeGen/X86/mult-alt-generic-x86_64.ll
+++ test/CodeGen/X86/mult-alt-generic-x86_64.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -no-integrated-inline-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64"
Index: test/CodeGen/X86/mult-alt-x86.ll
===================================================================
--- test/CodeGen/X86/mult-alt-x86.ll
+++ test/CodeGen/X86/mult-alt-x86.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -no-integrated-inline-as
 ; ModuleID = 'mult-alt-x86.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i686-pc-win32"
Index: test/CodeGen/X86/multiple-loop-post-inc.ll
===================================================================
--- test/CodeGen/X86/multiple-loop-post-inc.ll
+++ test/CodeGen/X86/multiple-loop-post-inc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s
+; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem -no-integrated-inline-as < %s | FileCheck %s
 ; rdar://7236213
 ;
 ; The scheduler's 2-address hack has been disabled, so there is
Index: test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll
===================================================================
--- test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll
+++ test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -std-compile-opts -o - | llc -o - | grep bork_directive | wc -l | grep 2
+; RUN: opt < %s -std-compile-opts -o - | llc -no-integrated-inline-as -o - | grep bork_directive | wc -l | grep 2
 
 ;; We don't want branch folding to fold asm directives.