Index: lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -395,9 +395,10 @@
   const MCInstrDesc &Desc = MI.getDesc();
 
   int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
-  int VDataRCID = -1;
-  if (VDataIdx != -1)
-    VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
+  if (VDataIdx == -1)
+    return -1;
+
+  int VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
 
   if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
     // For MUBUF/MTBUF instructions this hazard only exists if the
Index: test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
===================================================================
--- test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
+++ test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
@@ -7,9 +7,11 @@
 ; GCN-NEXT: ; BB#0:
 ; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
 ; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
-; GCN-NEXT: s_endpgm
+; GCN: s_endpgm
 define void @test_buffer_wbinvl1_vol() #0 {
   call void @llvm.amdgcn.buffer.wbinvl1.vol()
+; This used to crash in hazard recognizer
+  store i8 0, i8 addrspace(1)* undef, align 1
   ret void
 }