Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -823,7 +823,7 @@ FeatureCrypto, FeatureCRC]>; -def : ProcNoItin<"cortex-r52", [ARMv8r, ProcR52, +def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureFPAO]>; //===----------------------------------------------------------------------===// Index: lib/Target/ARM/ARMSchedule.td =================================================================== --- lib/Target/ARM/ARMSchedule.td +++ lib/Target/ARM/ARMSchedule.td @@ -364,3 +364,4 @@ include "ARMScheduleA8.td" include "ARMScheduleA9.td" include "ARMScheduleSwift.td" +include "ARMScheduleR52.td" Index: lib/Target/ARM/ARMScheduleR52.td =================================================================== --- /dev/null +++ lib/Target/ARM/ARMScheduleR52.td @@ -0,0 +1,983 @@ +//==- ARMScheduleR52.td - Cortex-R52 Scheduling Definitions -*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the SchedRead/Write data for the ARM Cortex-R52 processor. +// +//===----------------------------------------------------------------------===// + +// ===---------------------------------------------------------------------===// +// The Cortex-R52 is an in-order pipelined superscalar microprocessor with +// a 8 stage pipeline. It can issue maximum two instructions in each cycle. +// There are two ALUs, one LDST, one MUL and a non-pipelined integer DIV. +// A number of forwarding paths enable results of computations to be input +// to subsequent operations before they are written to registers. +// This scheduler is a MachineScheduler. See TargetSchedule.td for details. + +def CortexR52Model : SchedMachineModel { + let MicroOpBufferSize = 0; // R52 is in-order processor + let IssueWidth = 2; // 2 micro-ops dispatched per cycle + let LoadLatency = 1; // Optimistic, assuming no misses + let MispredictPenalty = 8; // A branch direction mispredict, including PFU + let PostRAScheduler = 1; // Enable PostRA scheduler pass. + let CompleteModel = 0; // Covers instructions applicable to cortex-r52. +} + + +//===----------------------------------------------------------------------===// +// Define each kind of processor resource and number available. + +// Modeling each pipeline as a ProcResource using the BufferSize = 0 since +// Cortex-R52 is an in-order processor. + +def R52UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU +def R52UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC +def R52UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division +def R52UnitLd : ProcResource<1> { let BufferSize = 0; } // Load/Store +def R52UnitB : ProcResource<1> { let BufferSize = 0; } // Branch +def R52UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU +def R52UnitFPMUL : ProcResource<2> { let BufferSize = 0; } // FP MUL +def R52UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP DIV + +// Cortex-R52 specific SchedReads +def R52Read_ISS : SchedRead; +def R52Read_EX1 : SchedRead; +def R52Read_EX2 : SchedRead; +def R52Read_WRI : SchedRead; +def R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe +def R52Read_F1 : SchedRead; +def R52Read_F2 : SchedRead; + + +//===----------------------------------------------------------------------===// +// Subtarget-specific SchedWrite types which map ProcResources and set latency. + +let SchedModel = CortexR52Model in { + +// ALU - Write occurs in Late EX2 (independent of whether shift was required) +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } +def : WriteRes { let Latency = 3; } + +// Compares +def : WriteRes { let Latency = 0; } +def : WriteRes { let Latency = 0; } +def : WriteRes { let Latency = 0; } + +// Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2) +def : WriteRes { + let Latency = 8; let ResourceCycles = [8]; // not pipelined +} + +// Loads +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } + +// Branches - LR written in Late EX2 +def : WriteRes { let Latency = 0; } +def : WriteRes { let Latency = 0; } +def : WriteRes { let Latency = 0; } + +// Misc +def : WriteRes { let Latency = 0; let NumMicroOps = 0; } +def : WriteRes { let Latency = 3; } + +def : ReadAdvance; // Operand needed in EX1 stage +def : ReadAdvance; // Shift operands needed in ISS + + +//===----------------------------------------------------------------------===// +// Subtarget-specific SchedReadWrites. + +// Forwarding information - based on when an operand is read +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + + +// Cortex-R52 specific SchedWrites for use with InstRW +def R52WriteMAC : SchedWriteRes<[R52UnitMAC]> { let Latency = 4; } +def R52WriteDIV : SchedWriteRes<[R52UnitDiv]> { + let Latency = 8; let ResourceCycles = [8]; // not pipelined +} +def R52WriteLd : SchedWriteRes<[R52UnitLd]> { let Latency = 4; } +def R52WriteST : SchedWriteRes<[R52UnitLd]> { let Latency = 4; } +def R52WriteAdr : SchedWriteRes<[]> { let Latency = 0; } +def R52WriteCC : SchedWriteRes<[]> { let Latency = 0; } +def R52WriteALU_EX1 : SchedWriteRes<[R52UnitALU]> { let Latency = 2; } +def R52WriteALU_EX2 : SchedWriteRes<[R52UnitALU]> { let Latency = 3; } +def R52WriteALU_WRI : SchedWriteRes<[R52UnitALU]> { let Latency = 4; } + +def R52WriteNoRSRC_EX2 : SchedWriteRes<[]> { let Latency = 3; } +def R52WriteNoRSRC_WRI : SchedWriteRes<[]> { let Latency = 4; } + +def R52WriteFPALU_F3 : SchedWriteRes<[R52UnitFPALU]> { let Latency = 4; } +def R52Write2FPALU_F3 : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> { + let Latency = 4; +} +def R52WriteFPALU_F4 : SchedWriteRes<[R52UnitFPALU]> { let Latency = 5; } +def R52Write2FPALU_F4 : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> { + let Latency = 5; +} +def R52WriteFPALU_F5 : SchedWriteRes<[R52UnitFPALU]> { let Latency = 6; } +def R52Write2FPALU_F5 : SchedWriteRes<[R52UnitFPALU, R52UnitFPALU]> { + let Latency = 6; +} +def R52WriteFPMUL_F5 : SchedWriteRes<[R52UnitFPMUL]> { let Latency = 6; } +def R52Write2FPMUL_F5 : SchedWriteRes<[R52UnitFPMUL, R52UnitFPMUL]> { + let Latency = 6; +} +def R52WriteFPMAC_F5 : SchedWriteRes<[R52UnitFPMUL, R52UnitFPALU]> { + let Latency = 11; // as it is internally two insns (MUL then ADD) +} +def R52Write2FPMAC_F5 : SchedWriteRes<[R52UnitFPMUL, R52UnitFPMUL, + R52UnitFPALU, R52UnitFPALU]> { + let Latency = 11; +} + +def R52WriteFPLd_F4 : SchedWriteRes<[R52UnitLd]> { let Latency = 5; } +def R52WriteFPST_F4 : SchedWriteRes<[R52UnitLd]> { let Latency = 5; } + +def R52WriteFPDIV_SP : SchedWriteRes<[R52UnitFPDIV]> { + let Latency = 7; // FP div takes fixed #cycles + let ResourceCycles = [7]; // is not pipelined + } +def R52WriteFPDIV_DP : SchedWriteRes<[R52UnitFPDIV]> { + let Latency = 17; + let ResourceCycles = [17]; +} + + +//===----------------------------------------------------------------------===// +// Subtarget-specific - map operands to SchedReadWrites + +def : InstRW<[WriteALU], (instrs COPY)>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], + (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", + "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16")>; + +def : InstRW<[R52WriteALU_EX1, R52Read_ISS], + (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi", + "t2MOVi", "t2MOV_ga_dyn")>; +def : InstRW<[R52WriteALU_EX2, R52Read_EX1], + (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel")>; +def : InstRW<[R52WriteLd,R52Read_ISS], + (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "SEL", "t2SEL")>; + +def : InstRW< [R52WriteALU_EX2, R52Read_ISS, R52Read_ISS], + (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", + "(t|t2)UBFX", "(t|t2)SBFX")>; + +// Saturating arithmetic +def : InstRW< [R52WriteALU_WRI, R52Read_EX1, R52Read_EX1], + (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT", + "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX", + "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD", + "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT", + "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX", + "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX","t2ABS")>; + +// Parallel arithmetic +def : InstRW< [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], + (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX", + "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8", + "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8", + "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>; + +// Flag setting. +def : InstRW< [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], + (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX", + "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16", + "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16", + "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16", + "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX", + "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>; + +// Sum of Absolute Difference +def : InstRW< [R52WriteALU_WRI, R52Read_ISS, R52Read_ISS, R52Read_ISS], + (instregex "USAD8", "t2USAD8", "tUSAD8","USADA8", "t2USADA8", "tUSADA8") >; + +// Integer Multiply +def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS], + (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", + "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL", + "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", + "t2SMULWB", "t2SMULWT", "t2SMUSD")>; + +// Multiply Accumulate +// Even for 64-bit accumulation (or Long), the single MAC is used (not ALUs). +// The store pipeline is used partly for 64-bit operations. +def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS, R52Read_ISS], + (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", + "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR", + "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX", + "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", + "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", + "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT", + "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX", + "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$", + "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT", + "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", + "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", + "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", + "t2SMLSLD", "t2SMLSLDX", "t2UMAAL")>; + +def : InstRW <[R52WriteDIV, R52Read_ISS, R52Read_ISS], + (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>; + +// Loads (except POST) with SHL > 2, or ror, require 2 extra cycles. +// However, that's non-trivial to specify, so we keep it uniform +def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_ISS], + (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)", + "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "t2LDREX", + "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)", + "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$", + "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", + "t2LDRpci_pic", "tLDRS(B|H)", "t2LDRDi8", "LDRD$", "LDA", "t2LDA")>; +def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_ISS], + (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)", + "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", + "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T", + "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", + "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T", + "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "MOVS?sr", "t2MOVS?sr")>; +def : InstRW<[R52WriteALU_WRI, R52Read_EX2], (instregex "MOVT", "t2MOVT")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri","ANDS?ri", + "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri", + "t2AD(C|D)S?ri", "t2ANDS?ri", "t2BICS?ri","t2CLZ", "t2EORri", "t2MVN", + "t2ORRri", "t2RSBS?ri", "t2SBCri")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "AD(C|D)S?rr", + "ANDS?rr", "BICS?rr", "CRC*", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr", + "t2AD(C|D)S?rr", "t2ANDS?rr", "t2BICS?rr", "t2CRC", "t2EORrr", "t2SBCrr")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], (instregex "AD(C|D)S?rsi", + "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi", + "t2AD(|D)S?rsi", "t2ANDS?rsi", "t2BICS?rsi", "t2EORrsi", "t2ORRrsi", "t2RSBrsi", "t2SBCrsi")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS, R52Read_ISS], + (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr", + "ORRrsrr", "RSBrsr", "RSCrsr", "SBCrsr")>; + +def : InstRW<[R52WriteALU_EX1], + (instregex "ADR", "MOVSi", "MOVSsi", "MOVST?i16*", "MVNS?s?i", "t2MOVS?si")>; + +def : InstRW<[R52WriteALU_EX1, R52Read_ISS], (instregex "ASRi", "RORS?i")>; +def : InstRW<[R52WriteALU_EX1, R52Read_ISS, R52Read_ISS], + (instregex "ASRr", "RORS?r", "LSR", "LSL")>; + +def : InstRW<[R52WriteCC, R52Read_EX1], (instregex "CMPri", "CMNri")>; +def : InstRW<[R52WriteCC, R52Read_EX1, R52Read_EX1], (instregex "CMPrr", "CMNzrr")>; +def : InstRW<[R52WriteCC, R52Read_EX1, R52Read_ISS], (instregex "CMPrsi", "CMNzrsi")>; +def : InstRW<[R52WriteCC, R52Read_EX1, R52Read_ISS, R52Read_ISS], (instregex "CMPrsr", "CMNzrsr")>; + +def : InstRW<[R52WriteALU_EX2, R52Read_ISS], + (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>; + +def : InstRW<[R52WriteCC, R52Read_ISS], (instregex "TST")>; + +def : InstRW<[R52WriteLd], (instregex "MRS", "MRSbanked")>; +def : InstRW<[R52WriteLd, R52Read_EX1], (instregex "MSR", "MSRbanked")>; + +//def : InstRW<[R52WriteLd, R52Read_ISS], (instregex "^LDRB?(_PRE_IMM|_POST_IMM)", "LDRrs")>; +//def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_ISS], (instregex "^LDRB?_PRE_REG", "LDRB?rr")>; +//def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_ISS], (instregex "^LDRB?_POST_REG")>; + +//def : InstRW<[R52WriteST, R52Read_ISS], (instregex "STRi12", "PICSTR")>; +//def : InstRW<[R52WriteST, R52WriteAdr, R52Read_ISS, R52Read_EX2], (instregex "t2STRB?_PRE_REG", "STRB?_PRE_REG")>; +//def : InstRW<[R52WriteST, R52WriteAdr, R52Read_ISS, R52Read_EX2], (instregex "t2STRB?_POST_REG", "STRB?_POST_REG")>; + + +// Integer Load, Multiple. +foreach Lat = 3-25 in { + def R52WriteILDM#Lat#Cy : SchedWriteRes<[R52UnitLd]> { + let Latency = Lat; + } + def R52WriteILDM#Lat#CyNo : SchedWriteRes<[]> { + let Latency = Lat; + let NumMicroOps = 0; + } +} +foreach NAddr = 1-16 in { + def R52ILDMAddr#NAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NAddr>; +} +def R52WriteILDMAddrNoWB : SchedWriteRes<[R52UnitLd]> { let Latency = 0; } +def R52WriteILDMAddrWB : SchedWriteRes<[R52UnitLd]>; +def R52WriteILDM : SchedWriteVariant<[ + SchedVar, + + SchedVar, + SchedVar, + + SchedVar, + SchedVar, + + SchedVar, + SchedVar, + + SchedVar, + SchedVar, + + SchedVar, + SchedVar, + + SchedVar, + SchedVar, + + SchedVar, + SchedVar, + +// Unknown number of registers, just use resources for two registers. + SchedVar +]> { let Variadic=1; } + +// Integer Store, Multiple +def R52WriteIStIncAddr : SchedWriteRes<[R52UnitLd]> { + let Latency = 4; + let NumMicroOps = 2; +} +foreach NumAddr = 1-16 in { + def R52WriteISTM#NumAddr : WriteSequence<[R52WriteIStIncAddr], NumAddr>; +} +def R52WriteISTM : SchedWriteVariant<[ + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + // Unknow number of registers, just use resources for two registers. + SchedVar +]>; + +def : InstRW<[R52WriteILDM, R52Read_ISS], + (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$", + "(t|sys)LDM(IA|DA|DB|IB)$")>; +def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], + (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; +def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS], + (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>; + +// Integer Store, Single Element +def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], + (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", "SRS", "t2SRS", + "t2SRSDB", "t2STREX", "t2STREXB", "t2STREXD", "t2STREXH", "t2STR(i12|i8|s)$", + "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>; + +def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], + (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)", + "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)", + "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)", + "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>; + +// Integer Store, Dual +def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2], + (instregex "STRD$", "t2STRDi8", "STL", "t2STRD$", "t2STL")>; +def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2], + (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>; + +def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2], + (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; +def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2], + (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", + "PUSH", "tPUSH")>; + +// LDRLIT pseudo instructions, they expand to LDR + PICADD +def : InstRW<[R52WriteLd], + (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>; +// LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR +def : InstRW<[R52WriteLd], (instregex "LDRLIT_ga_pcrel_ldr")>; + + + +//===----------------------------------------------------------------------===// +// VFP, Floating Point Support +def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fd|hd)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "VABD(fq|hq)")>; + +def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(D|S|H)")>; +def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VABS(fd|hd)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F1], (instregex "VABS(fq|hq)")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fd|hd)")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F1], (instregex "(VACGE|VACGT)(fq|hq)")>; + +def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(D|S|H|fd|hd)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1], (instregex "(VADD|VSUB)(fq|hq)")>; + +def : InstRW<[R52WriteFPDIV_SP, R52Read_F0, R52Read_F0], (instregex "VDIV(S|H)")>; +def : InstRW<[R52WriteFPDIV_DP, R52Read_F0, R52Read_F0], (instregex "VDIVD")>; + +def : InstRW<[R52WriteFPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], + (instregex "(VFMA|VFMS|VFNMA|VFNMS)(D|H|S)")>; + +def : InstRW<[R52WriteFPLd_F4, R52Read_ISS, R52Read_F1], (instregex "VLDR")>; +def : InstRW<[R52WriteFPST_F4, R52Read_ISS, R52Read_F1], (instregex "VSTR")>; + + +//===----------------------------------------------------------------------===// +// Neon Support + +// vector multiple load stores +foreach NumAddr = 1-16 in { + def R52LMAddrPred#NumAddr : + SchedPredicate<"MI->getNumOperands() == "#NumAddr>; +} +foreach Lat = 1-32 in { + def R52WriteLM#Lat#Cy : SchedWriteRes<[]> { + let Latency = Lat; + } +} +foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue + def R52ReserveLd#Num#Cy : SchedWriteRes<[R52UnitLd]> { + let Latency = 0; + let NumMicroOps = Num; + let ResourceCycles = [Num]; + } +} +def R52WriteVLDM : SchedWriteVariant<[ + // 1 D reg + SchedVar, + SchedVar, + + // 2 D reg + SchedVar, + SchedVar, + + // 3 D reg + SchedVar, + SchedVar, + + // 4 D reg + SchedVar, + SchedVar, + + // 5 D reg + SchedVar, + SchedVar, + + // 6 D reg + SchedVar, + SchedVar, + + // 7 D reg + SchedVar, + SchedVar, + + // 8 D reg + SchedVar, + SchedVar, + // unknown number of reg. + SchedVar +]> { let Variadic=1;} + +// variable stores. Cannot dual-issue +def R52WriteSTM5 : SchedWriteRes<[R52UnitLd]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1]; +} +def R52WriteSTM6 : SchedWriteRes<[R52UnitLd]> { + let Latency = 6; + let NumMicroOps = 4; + let ResourceCycles = [2]; +} +def R52WriteSTM7 : SchedWriteRes<[R52UnitLd]> { + let Latency = 7; + let NumMicroOps = 6; + let ResourceCycles = [3]; +} +def R52WriteSTM8 : SchedWriteRes<[R52UnitLd]> { + let Latency = 8; + let NumMicroOps = 8; + let ResourceCycles = [4]; +} +def R52WriteSTM9 : SchedWriteRes<[R52UnitLd]> { + let Latency = 9; + let NumMicroOps = 10; + let ResourceCycles = [5]; +} +def R52WriteSTM10 : SchedWriteRes<[R52UnitLd]> { + let Latency = 10; + let NumMicroOps = 12; + let ResourceCycles = [6]; +} +def R52WriteSTM11 : SchedWriteRes<[R52UnitLd]> { + let Latency = 11; + let NumMicroOps = 14; + let ResourceCycles = [7]; +} +def R52WriteSTM12 : SchedWriteRes<[R52UnitLd]> { + let Latency = 12; + let NumMicroOps = 16; + let ResourceCycles = [8]; +} +def R52WriteSTM13 : SchedWriteRes<[R52UnitLd]> { + let Latency = 13; + let NumMicroOps = 18; + let ResourceCycles = [9]; +} +def R52WriteSTM14 : SchedWriteRes<[R52UnitLd]> { + let Latency = 14; + let NumMicroOps = 20; + let ResourceCycles = [10]; +} +def R52WriteSTM15 : SchedWriteRes<[R52UnitLd]> { + let Latency = 15; + let NumMicroOps = 22; + let ResourceCycles = [11]; +} + +def R52WriteSTM : SchedWriteVariant<[ + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + SchedVar, + // unknown number of registers, just use resources for two + SchedVar +]>; + +// Vector Load/Stores. Can issue only in slot-0. Can dual-issue with +// another instruction in slot-1, but only in the last issue. +def R52WriteVLD1Mem : SchedWriteRes<[R52UnitLd]> { let Latency = 5;} +def R52WriteVLD2Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2]; +} +def R52WriteVLD3Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [3]; +} +def R52WriteVLD4Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 8; + let NumMicroOps = 7; + let ResourceCycles = [4]; +} +def R52WriteVST1Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def R52WriteVST2Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [2]; +} +def R52WriteVST3Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 7; + let NumMicroOps = 5; + let ResourceCycles = [3]; +} +def R52WriteVST4Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 8; + let NumMicroOps = 7; + let ResourceCycles = [4]; +} +def R52WriteVST5Mem : SchedWriteRes<[R52UnitLd]> { + let Latency = 9; + let NumMicroOps = 9; + let ResourceCycles = [5]; +} + + +def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v8i8|v4i16|v2i32)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v16i8|v8i16|v4i32)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABAL(u|s)(v8i16|v4i32|v2i64)")>; + +def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v8i8|v4i16|v2i32)")>; +def : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v16i8|v8i16|v4i32)")>; +def : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABDL(u|s)(v16i8|v8i16|v4i32)")>; + +def : InstRW<[R52Write2FPALU_F4, R52Read_F1], (instregex "VABS(v16i8|v8i16|v4i32)")>; + +def : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], + (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)")>; +def : InstRW<[R52Write2FPALU_F4, R52Read_F2, R52Read_F2], + (instregex "(VADD|VSUB)(v16i8|v8i16|v4i32|v2i64)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F2, R52Read_F2], + (instregex "(VADDHN|VRADDHN|VSUBHN|VRSUBHN)(v8i8|v4i16|v2i32)")>; + +def : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], + (instregex "VADDL", "VADDW", "VSUBL", "VSUBW")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)d")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_F2], (instregex "VBICi(v4i16|v2i32)")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q")>; + +def : InstRW<[R52Write2FPALU_F3, R52Read_F2], (instregex "VBICi(v8i16|v4i32)")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], + (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>; +def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], + (instregex "VCVT", "VSITO", "VUITO", "VTO")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)d")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_ISS], (instregex "VDUP(8|16|32)q")>; +def : InstRW<[R52WriteFPALU_F3, R52Read_F1], (instregex "VDUPLN(8|16|32)d")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_F1], (instregex "VDUPLN(8|16|32)q")>; + +def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VEXTd(8|16|32)", "VSEL")>; +def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F1], (instregex "VEXTq(8|16|32|64)")>; + +def : InstRW<[R52WriteFPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "(VFMA|VFMS)(f|h)d")>; +def : InstRW<[R52Write2FPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "(VFMA|VFMS)(f|h)q")>; + +def : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD|VHSUB)(u|s)(v8i8|v4i16|v2i32)")>; +def : InstRW<[R52Write2FPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD|VHSUB)(u|s)(v16i8|v8i16|v4i32)")>; + +def : InstRW<[R52WriteVLDM], (instregex "VLDM[SD](IA|DB)$")>; +def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VMAX", "VMIN", "VPMAX", "VPMIN")>; +def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VMOV", "VORR", "VORN", "VREV")>; +def : InstRW<[R52WriteNoRSRC_WRI], (instregex "VMRS")>; +def : InstRW<[R52WriteFPMUL_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VMUL", "VNMUL", "VMLA")>; +def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VNEG")>; +def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VPADDi")>; +def : InstRW<[R52Write2FPALU_F4, R52Read_F1, R52Read_F1], (instregex "VPADAL", "VPADDL")>; +def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F1], (instregex "VQABS(v16i8|v8i16|v4i32|v2i64)")>; +def : InstRW<[R52WriteFPALU_F5, R52Read_F2, R52Read_F2], + (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)")>; +def : InstRW<[R52Write2FPALU_F5, R52Read_F2, R52Read_F2], + (instregex "(VQADD|VQSUB)(u|s)(v16i8|v8i16|v4i32|v2i64)")>; +def : InstRW<[R52Write2FPMAC_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VQDMLAL", "VQDMLSL")>; +def : InstRW<[R52WriteFPMUL_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VQDMUL","VQRDMUL")>; +def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1], + (instregex "VQMOVN", "VQNEG", "VQSHL", "VQSHRN")>; +def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VRSHL", "VRSHR", "VRSHRN", "VTB")>; +def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")>; + +//--- +// VLDx. Vector Loads +//--- +// 1-element structure load +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD1d(8|16|32|64)$")>; +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD1q(8|16|32|64)$")>; +def : InstRW<[R52WriteVLD3Mem, R52Read_ISS], (instregex "VLD1d(8|16|32|64)T$")>; +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD1d(8|16|32|64)Q$")>; +def : InstRW<[R52WriteVLD3Mem, R52Read_ISS], (instregex "VLD1d64TPseudo$")>; +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD1d64QPseudo$")>; + +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD1(LN|DUP)d(8|16|32)$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD1LNdAsm_(8|16|32)")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD1(LN|DUP)q(8|16|32)Pseudo$")>; + +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1d(8|16|32|64)wb")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1q(8|16|32|64)wb")>; +def : InstRW<[R52WriteVLD3Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1d(8|16|32|64)Twb")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1d(8|16|32|64)Qwb")>; +def : InstRW<[R52WriteVLD3Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1d64TPseudoWB")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1d64QPseudoWB")>; + +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1LNd(8|16|32)_UPD")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1LNdWB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1DUP(d|q)(8|16|32)wb")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD1(LN|DUP)q(8|16|32)Pseudo_UPD")>; + +// 2-element structure load +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD2(d|b)(8|16|32)$")>; +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD2q(8|16|32)$")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2(d|b)(8|16|32)wb")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2q(8|16|32)wb")>; +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD2q(8|16|32)Pseudo$")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2q(8|16|32)PseudoWB")>; + +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2LNd(8|16|32)$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2LNdAsm_(8|16|32)$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2LNq(16|32)$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2LNqAsm_(16|32)$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2DUPd(8|16|32)$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2DUPd(8|16|32)x2$")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2LNd(8|16|32)Pseudo")>; +def : InstRW<[R52WriteVLD1Mem, R52Read_ISS], (instregex "VLD2LNq(16|32)Pseudo")>; + +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2LNd(8|16|32)_UPD")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2LNdWB_(fixed|register)_Asm_(8|16|32)")>; + +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2LNq(16|32)_UPD")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2LNqWB_(fixed|register)_Asm_(16|32)")>; + +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2DUPd(8|16|32)wb")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2DUPd(8|16|32)x2wb")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2LNd(8|16|32)Pseudo_UPD")>; +def : InstRW<[R52WriteVLD1Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD2LNq(16|32)Pseudo_UPD")>; + +// 3-element structure load +def : InstRW<[R52WriteVLD3Mem, R52Read_ISS], (instregex "VLD3(d|q)(8|16|32)$")>; +def : InstRW<[R52WriteVLD3Mem, R52Read_ISS], (instregex "VLD3(d|q)Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVLD3Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(d|q)(8|16|32)_UPD")>; +def : InstRW<[R52WriteVLD3Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVLD3Mem, R52Read_ISS], (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo")>; +def : InstRW<[R52WriteVLD3Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>; + +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)(8|16|32)$")>; +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>; + +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>; + +// 4-element structure load +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD4(d|q)(8|16|32)$")>; +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD4(d|q)Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVLD4Mem, R52Read_ISS], (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD4(d|q)(8|16|32)_UPD")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD4(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVLD4Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>; + + +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$")>; +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD4(LN|DUP)(d|q)Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD4LN(d|q)(8|16|32)Pseudo$")>; +def : InstRW<[R52WriteVLD2Mem, R52Read_ISS], (instregex "VLD4DUPd(8|16|32)Pseudo$")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD4(LN|DUP)(d|q)(8|16|32)_UPD")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD4(LN|DUP)(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVLD2Mem, R52WriteAdr, R52Read_ISS], (instregex "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>; + +//--- +// VSTx. Vector Stores +//--- +// 1-element structure store +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST1q(8|16|32|64)$")>; +def : InstRW<[R52WriteVST3Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)T$")>; +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)Q$")>; +def : InstRW<[R52WriteVST3Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d64TPseudo$")>; +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST1d64QPseudo$")>; + +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1LNd(8|16|32)$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1LNdAsm_(8|16|32)$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST1LNq(8|16|32)Pseudo$")>; + +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)wb")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1q(8|16|32|64)wb")>; +def : InstRW<[R52WriteVST3Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)Twb")>; +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d(8|16|32|64)Qwb")>; +def : InstRW<[R52WriteVST3Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d64TPseudoWB")>; +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1d64QPseudoWB")>; + +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1LNd(8|16|32)_UPD")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1LNdWB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST1LNq(8|16|32)Pseudo_UPD")>; + +// 2-element structure store +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST2(d|b)(8|16|32)$")>; +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)$")>; +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)Pseudo$")>; + +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNdAsm_(8|16|32)$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)Pseudo$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNqAsm_(16|32)$")>; +def : InstRW<[R52WriteVST1Mem, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)Pseudo$")>; + +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2(d|b)(8|16|32)wb")>; +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)wb")>; +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2q(8|16|32)PseudoWB")>; + +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)_UPD")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNdWB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNd(8|16|32)Pseudo_UPD")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)_UPD")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNqWB_(fixed|register)_Asm_(16|32)")>; +def : InstRW<[R52WriteVST1Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST2LNq(16|32)Pseudo_UPD")>; + +// 3-element structure store +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)(8|16|32)$")>; +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVST4Mem, R52Read_ISS, R52Read_F2], (instregex "VST3d(8|16|32)(oddP|P)seudo$")>; + +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNdAsm_(8|16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)Pseudo$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNqAsm_(16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)Pseudo$")>; + +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)(8|16|32)_UPD$")>; +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)WB_(fixed|register)_Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVST4Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>; + +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)_UPD$")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNdWB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNd(8|16|32)Pseudo_UPD$")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)_UPD$")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNqWB_(fixed|register)_Asm_(16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST3LNq(16|32)Pseudo_UPD$")>; + +// 4-element structure store +def : InstRW<[R52WriteVST5Mem, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)(8|16|32)$")>; +def : InstRW<[R52WriteVST5Mem, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)Asm_(8|16|32)$")>; +def : InstRW<[R52WriteVST5Mem, R52Read_ISS, R52Read_F2], (instregex "VST4d(8|16|32)Pseudo$")>; + +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNdAsm_(8|16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)Pseudo$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNqAsm_(16|32)$")>; +def : InstRW<[R52WriteVST2Mem, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)Pseudo$")>; + +def : InstRW<[R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)(8|16|32)_UPD")>; +def : InstRW<[R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)WB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVST5Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD")>; + +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)_UPD")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNdWB_(fixed|register)_Asm_(8|16|32)")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNd(8|16|32)Pseudo_UPD")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)_UPD")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNqWB_(fixed|register)_Asm_(16|32)")>; +def : InstRW<[R52WriteVST2Mem, R52WriteAdr, R52Read_ISS, R52Read_F2], (instregex "VST4LNq(16|32)Pseudo_UPD")>; + +} // R52 SchedModel Index: test/CodeGen/ARM/cortexr52-misched-basic.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -0,0 +1,39 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC +; +; Check the latency for instructions for both generic and cortex-r52. +; Cortex-r52 machine model will cause the div to be sceduled before eor +; as div takes more cycles to compute than eor. +; +; CHECK: ********** MI Scheduling ********** +; CHECK: foo:BB#0 entry +; CHECK: EORrr +; GENERIC: Latency : 1 +; R52_SCHED: Latency : 3 +; CHECK: MLA +; GENERIC: Latency : 1 +; R52_SCHED: Latency : 4 +; CHECK: SDIV +; GENERIC: Latency : 1 +; R52_SCHED: Latency : 8 +; CHECK: ** Final schedule for BB#0 *** +; GENERIC: EORrr +; GENERIC: SDIV +; R52_SCHED: SDIV +; R52_SCHED: EORrr +; CHECK: ********** INTERVALS ********** + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv8r-arm-none-eabi" + +; Function Attrs: norecurse nounwind readnone +define hidden i32 @foo(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 { +entry: + %xor = xor i32 %c, %b + %mul = mul nsw i32 %xor, %c + %add = add nsw i32 %mul, %a + %div = sdiv i32 %a, %b + %sub = sub i32 %add, %div + ret i32 %sub +}