Index: lib/Sema/SemaChecking.cpp
===================================================================
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -4191,7 +4191,7 @@
 
     SmallVector<int, 5> Ranges;
     if (FiveFields)
-      Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 7, 15, 15});
+      Ranges.append({IsAArch64Builtin ? 1 : 15, 7, 15, 15, 7});
     else
       Ranges.append({15, 7, 15});
 
Index: test/Sema/aarch64-special-register.c
===================================================================
--- test/Sema/aarch64-special-register.c
+++ test/Sema/aarch64-special-register.c
@@ -41,7 +41,7 @@
 }
 
 unsigned rsr_2() {
-  return __builtin_arm_rsr("0:1:2:3:4");
+  return __builtin_arm_rsr("0:1:15:15:4");
 }
 
 void *rsrp_2() {
@@ -49,7 +49,7 @@
 }
 
 unsigned long rsr64_2() {
-  return __builtin_arm_rsr64("0:1:2:3:4");
+  return __builtin_arm_rsr64("0:1:15:15:4");
 }
 
 void wsr_3(unsigned v) {
@@ -68,6 +68,18 @@
   return __builtin_arm_rsr("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
 
+unsigned rsr_4() {
+  return __builtin_arm_rsr("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_5() {
+  return __builtin_arm_rsr("0:8:1:2:3"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_6() {
+  return __builtin_arm_rsr("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
+}
+
 void *rsrp_3() {
   return __builtin_arm_rsrp("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
@@ -75,3 +87,15 @@
 unsigned long rsr64_3() {
   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
+
+unsigned long rsr64_4() {
+  return __builtin_arm_rsr64("0:1:2:3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_5() {
+  return __builtin_arm_rsr64("0:8:2:3:4"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_6() {
+  return __builtin_arm_rsr64("0:1:16:16:2"); //expected-error {{invalid special register for builtin}}
+}
Index: test/Sema/arm-special-register.c
===================================================================
--- test/Sema/arm-special-register.c
+++ test/Sema/arm-special-register.c
@@ -41,7 +41,7 @@
 }
 
 unsigned rsr_2() {
-  return __builtin_arm_rsr("cp0:1:c2:c3:4");
+  return __builtin_arm_rsr("cp0:1:c15:c15:4");
 }
 
 void *rsrp_2() {
@@ -73,13 +73,25 @@
 }
 
 unsigned long rsr64_3() {
-  return __builtin_arm_rsr64("cp0:1:c2");
+  return __builtin_arm_rsr64("cp0:1:c15");
 }
 
 unsigned rsr_4() {
   return __builtin_arm_rsr("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
 }
 
+unsigned rsr_5() {
+  return __builtin_arm_rsr("cp0:1:c2:c3:8"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_6() {
+  return __builtin_arm_rsr("cp0:8:c1:c2:3"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned rsr_7() {
+  return __builtin_arm_rsr("cp0:1:c16:c16:2"); //expected-error {{invalid special register for builtin}}
+}
+
 void *rsrp_4() {
   return __builtin_arm_rsrp("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
 }
@@ -87,3 +99,11 @@
 unsigned long rsr64_4() {
   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
 }
+
+unsigned long rsr64_5() {
+  return __builtin_arm_rsr64("cp0:8:c1"); //expected-error {{invalid special register for builtin}}
+}
+
+unsigned long rsr64_6() {
+  return __builtin_arm_rsr64("cp0:1:c16"); //expected-error {{invalid special register for builtin}}
+}