Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7305,7 +7305,7 @@
   }
 
   // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
-  if (N0.getOpcode() == ISD::SELECT) {
+  if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) {
     EVT SrcVT = N0.getValueType();
     if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
         TLI.isTruncateFree(SrcVT, VT)) {
Index: test/CodeGen/X86/select.ll
===================================================================
--- test/CodeGen/X86/select.ll
+++ test/CodeGen/X86/select.ll
@@ -515,6 +515,28 @@
   ret i32 %tmp2
 }
 
+define void @clamp(float* %src, i16* %dst) {
+; verify that 2 select will not became 3 cmovs
+; fixes pr29002
+entry:
+; CHECK-LABEL: clamp:
+; CHECK:       ## BB#0:
+; CHECK: cmovlel
+; CHECK: cmovgew
+; CHECK-NOT: cmov
+; CHECK: retq
+  %ld = load float, float* %src, align 4
+  %mul = fmul float %ld, 3.276700e+04
+  %conv = fptosi float %mul to i32
+  %cmp = icmp sgt i32 %conv, 32767
+  %sel1 = select i1 %cmp, i32 32767, i32 %conv
+  %cmp2 = icmp slt i32 %sel1, -32768
+  %sel2 = select i1 %cmp2, i32 -32768, i32 %sel1
+  %conv6 = trunc i32 %sel2 to i16
+  store i16 %conv6, i16* %dst, align 2
+  ret void
+}
+
 define void @test19() {
 ; This is a massive reduction of an llvm-stress test case that generates
 ; interesting chains feeding setcc and eventually a f32 select operation. This