Index: lib/Target/AArch64/AArch64.td =================================================================== --- lib/Target/AArch64/AArch64.td +++ lib/Target/AArch64/AArch64.td @@ -61,11 +61,6 @@ "Reserve X18, making it unavailable " "as a GPR">; -def FeatureMergeNarrowZeroSt : SubtargetFeature<"merge-narrow-zero-st", - "MergeNarrowZeroStores", "true", - "Merge narrow zero store " - "instructions">; - def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", "Use alias analysis during codegen">; @@ -182,7 +177,6 @@ FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, - FeatureMergeNarrowZeroSt, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, @@ -253,7 +247,6 @@ FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, - FeatureMergeNarrowZeroSt, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp =================================================================== --- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -1699,8 +1699,7 @@ UsedRegs.resize(TRI->getNumRegs()); bool Modified = false; - bool enableNarrowZeroStOpt = - Subtarget->mergeNarrowStores() && !Subtarget->requiresStrictAlign(); + bool enableNarrowZeroStOpt = !Subtarget->requiresStrictAlign(); for (auto &MBB : Fn) Modified |= optimizeBlock(MBB, enableNarrowZeroStOpt); Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -71,7 +71,6 @@ // StrictAlign - Disallow unaligned memory accesses. bool StrictAlign = false; - bool MergeNarrowZeroStores = false; bool UseAA = false; bool PredictableSelectIsExpensive = false; bool BalanceFPOps = false; @@ -179,7 +178,6 @@ bool hasCrypto() const { return HasCrypto; } bool hasCRC() const { return HasCRC; } bool hasRAS() const { return HasRAS; } - bool mergeNarrowStores() const { return MergeNarrowZeroStores; } bool balanceFPOps() const { return BalanceFPOps; } bool predictableSelectIsExpensive() const { return PredictableSelectIsExpensive; Index: test/CodeGen/AArch64/arm64-narrow-st-merge.ll =================================================================== --- test/CodeGen/AArch64/arm64-narrow-st-merge.ll +++ test/CodeGen/AArch64/arm64-narrow-st-merge.ll @@ -1,6 +1,11 @@ -; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK -; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK -; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=kryo -verify-machineinstrs | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -mtriple aarch64--none-eabi -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=kryo -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cyclone -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=exynos-m1 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=exynos-m2 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=vulcan -verify-machineinstrs | FileCheck %s ; CHECK-LABEL: Strh_zero ; CHECK: str wzr