Index: include/llvm/IR/IntrinsicsPowerPC.td =================================================================== --- include/llvm/IR/IntrinsicsPowerPC.td +++ include/llvm/IR/IntrinsicsPowerPC.td @@ -806,6 +806,24 @@ def int_ppc_vsx_xviexpsp : PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>; +def int_ppc_vsx_xvxexpdp : + PowerPC_VSX_Intrinsic<"xvxexpdp", [llvm_v2i64_ty], + [llvm_v2f64_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxexpsp : + PowerPC_VSX_Intrinsic<"xvxexpsp", [llvm_v4i32_ty], + [llvm_v4f32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxsigdp : + PowerPC_VSX_Intrinsic<"xvxsigdp", [llvm_v2i64_ty], + [llvm_v2f64_ty], [IntrNoMem]>; +def int_ppc_vsx_xvxsigsp : + PowerPC_VSX_Intrinsic<"xvxsigsp", [llvm_v4i32_ty], + [llvm_v4f32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvtstdcdp : + PowerPC_VSX_Intrinsic<"xvtstdcdp", [llvm_v2i64_ty], + [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvtstdcsp : + PowerPC_VSX_Intrinsic<"xvtstdcsp", [llvm_v4i32_ty], + [llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// Index: lib/Target/PowerPC/PPCInstrVSX.td =================================================================== --- lib/Target/PowerPC/PPCInstrVSX.td +++ lib/Target/PowerPC/PPCInstrVSX.td @@ -2196,10 +2196,18 @@ IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>; // Vector Extract Exponent/Significand DP/SP - def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, []>; - def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, []>; - def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, []>; - def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, []>; + def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, + [(set v2i64: $XT, + (int_ppc_vsx_xvxexpdp v2f64:$XB))]>; + def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, + [(set v4i32: $XT, + (int_ppc_vsx_xvxexpsp v4f32:$XB))]>; + def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, + [(set v2i64: $XT, + (int_ppc_vsx_xvxsigdp v2f64:$XB))]>; + def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, + [(set v4i32: $XT, + (int_ppc_vsx_xvxsigsp v4f32:$XB))]>; //===--------------------------------------------------------------------===// @@ -2220,10 +2228,14 @@ let UseVSXReg = 1 in { def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), - "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>; + "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, + [(set v4i32: $XT, + (int_ppc_vsx_xvtstdcsp v4f32:$XB, imm:$DCMX))]>; def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5, (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), - "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>; + "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, + [(set v2i64: $XT, + (int_ppc_vsx_xvtstdcdp v2f64:$XB, imm:$DCMX))]>; } // UseVSXReg = 1 //===--------------------------------------------------------------------===// Index: test/CodeGen/PowerPC/vsx-p9.ll =================================================================== --- test/CodeGen/PowerPC/vsx-p9.ll +++ test/CodeGen/PowerPC/vsx-p9.ll @@ -190,4 +190,76 @@ ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>) +; Function Attrs: nounwind readnone +define <4 x i32> @testXVXEXPSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testXVXEXPSP +; CHECK: xvxexpsp 34, 34 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVXEXPDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testXVXEXPDP +; CHECK xvxexpdp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testXVXSIGSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testXVXSIGSP +; CHECK xvxsigsp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVXSIGDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testXVXSIGDP +; CHECK xvxsigdp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testXVTSTDCSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 127) + ret <4 x i32> %0 +; CHECK-LABEL: testXVTSTDCSP +; CHECK: xvtstdcsp 34, 34, 127 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 %b) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVTSTDCDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 127) + ret <2 x i64> %0 +; CHECK-LABEL: testXVTSTDCDP +; CHECK: xvtstdcdp 34, 34, 127 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b) + declare void @sink(...)