Index: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
@@ -438,7 +438,7 @@
   }
   case Instruction::GetElementPtr: {
     Address SavedAddr = Addr;
-    uint64_t TmpOffset = Addr.getOffset();
+    int64_t TmpOffset = Addr.getOffset();
     // Iterate through the GEP folding the constants into offsets where
     // we can.
     gep_type_iterator GTI = gep_type_begin(U);
@@ -756,7 +756,7 @@
   if (Addr.isFIBase()) {
     unsigned FI = Addr.getFI();
     unsigned Align = 4;
-    unsigned Offset = Addr.getOffset();
+    int64_t Offset = Addr.getOffset();
     MachineFrameInfo &MFI = MF->getFrameInfo();
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
@@ -807,7 +807,7 @@
   if (Addr.isFIBase()) {
     unsigned FI = Addr.getFI();
     unsigned Align = 4;
-    unsigned Offset = Addr.getOffset();
+    int64_t Offset = Addr.getOffset();
     MachineFrameInfo &MFI = MF->getFrameInfo();
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
Index: llvm/trunk/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -fast-isel -disable-fp-elim -relocation-model=pic < %s
+
+; Test that negative array access don't crash constant synthesis when fast isel
+; generates negative offsets.
+
+define i16 @test() {
+  %a = alloca [4 x i16], align 4
+  %arrayidx = getelementptr inbounds [4 x i16], [4 x i16]* %a, i32 0, i32 -2
+  %b = load i16, i16* %arrayidx, align 2
+  ret i16 %b
+}
+
+define void @test2() {
+  %a = alloca [4 x i16], align 4
+  %arrayidx = getelementptr inbounds [4 x i16], [4 x i16]* %a, i32 0, i32 -2
+  store i16 2, i16* %arrayidx, align 2
+  ret void
+}