Index: test/CodeGen/builtins-ppc-p9vector.c
===================================================================
--- test/CodeGen/builtins-ppc-p9vector.c
+++ test/CodeGen/builtins-ppc-p9vector.c
@@ -700,6 +700,34 @@
 // CHECK-NEXT: ret <8 x i16>
   return vec_popcnt (vusa);
 }
+vector double test55(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-BE-NEXT: ret <2 x double>
+// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-NEXT: ret <2 x double>
+  return vec_insert_exp (vda,vulb);
+}
+vector double test56(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-BE-NEXT: ret <2 x double>
+// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-NEXT: ret <2 x double>
+  return vec_insert_exp (vula, vulb);
+}
+vector float test57(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-BE-NEXT: ret <4 x float>
+// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-NEXT: ret <4 x float>
+  return vec_insert_exp (vfa,vuib);
+}
+vector float test58(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-BE-NEXT: ret <4 x float>
+// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-NEXT: ret <4 x float>
+  return vec_insert_exp (vuia,vuib);
+}
 signed int test59(void) {
 // CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
 // CHECK-BE-NEXT: ret i32
@@ -775,31 +803,3 @@
 // CHECK-NEXT: ret <1 x i128>
   return vec_parity_lsbb (vsi128a);
 }
-vector double test55(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-BE-NEXT: ret <2 x double>
-// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-NEXT: ret <2 x double>
-  return vec_insert_exp (vda,vulb);
-}
-vector double test56(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-BE-NEXT: ret <2 x double>
-// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-NEXT: ret <2 x double>
-  return vec_insert_exp (vula, vulb);
-}
-vector float test57(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-BE-NEXT: ret <4 x float>
-// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-NEXT: ret <4 x float>
-  return vec_insert_exp (vfa,vuib);
-}
-vector float test58(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-BE-NEXT: ret <4 x float>
-// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-NEXT: ret <4 x float>
-  return vec_insert_exp (vuia,vuib);
-}