Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -359,6 +359,8 @@ setOperationAction(ISD::FP_TO_SINT, VT, Expand); setOperationAction(ISD::FP_TO_UINT, VT, Expand); setOperationAction(ISD::MUL, VT, Expand); + setOperationAction(ISD::MULHU, VT, Expand); + setOperationAction(ISD::MULHS, VT, Expand); setOperationAction(ISD::OR, VT, Expand); setOperationAction(ISD::SHL, VT, Expand); setOperationAction(ISD::SRA, VT, Expand); Index: test/CodeGen/AMDGPU/sdiv.ll =================================================================== --- test/CodeGen/AMDGPU/sdiv.ll +++ test/CodeGen/AMDGPU/sdiv.ll @@ -156,3 +156,16 @@ ; store i64 %result, i64 addrspace(1)* %out, align 8 ; ret void ; } + +; FUNC-LABEL: @scalarize_mulhs_4xi32 +; SI: v_mul_hi_i32 +; SI: v_mul_hi_i32 +; SI: v_mul_hi_i32 +; SI: v_mul_hi_i32 + +define void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { + %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 + %2 = sdiv <4 x i32> %1, + store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 + ret void +} Index: test/CodeGen/AMDGPU/udiv.ll =================================================================== --- test/CodeGen/AMDGPU/udiv.ll +++ test/CodeGen/AMDGPU/udiv.ll @@ -145,3 +145,17 @@ store i32 %result.ext, i32 addrspace(1)* %out ret void } + +; FUNC-LABEL: @scalarize_mulhu_4xi32 +; SI: v_mul_hi_u32 +; SI: v_mul_hi_u32 +; SI: v_mul_hi_u32 +; SI: v_mul_hi_u32 + +define void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { + %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 + %2 = udiv <4 x i32> %1, + store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 + ret void +} +