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[X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64
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Authored by RKSimon on Oct 26 2016, 1:55 PM.

Details

Summary

With DQI but without VLX, lower v2i64 and v4i64 MUL operations with v8i64 MUL (vpmullq).

Updated cost table accordingly.

Diff Detail

Event Timeline

RKSimon updated this revision to Diff 75943.Oct 26 2016, 1:55 PM
RKSimon retitled this revision from to [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64.
RKSimon updated this object.
RKSimon added reviewers: delena, igorb.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
igorb accepted this revision.Oct 27 2016, 7:01 AM
igorb edited edge metadata.

LGTM

lib/Target/X86/X86ISelLowering.cpp
19858 ↗(On Diff #75943)

Hello,
It is possible to implement this logic in td file, similar to multiclass avx512_var_shift_w_lowering<..> implementation.

This revision is now accepted and ready to land.Oct 27 2016, 7:01 AM
This revision was automatically updated to reflect the committed changes.