Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -27356,6 +27356,39 @@
       Other = LHS;
     }
 
+    if (Other.getNode() && Other.getOpcode() == ISD::TRUNCATE &&
+        Other.getOperand(0).getOpcode() == ISD::SUB && isUnsignedIntSetCC(CC)) {
+      //  x >= y ? x - y : 0, where y is wider then x. We can truncate y
+      //  to x, because it is only used if it is less than x.
+      SDValue SubXY = Other.getOperand(0);
+      EVT ExtType = SubXY.getValueType();
+
+      SDValue SubLHS = SubXY.getOperand(0), SubRHS = SubXY.getOperand(1);
+      SDValue CondLHS = Cond.getOperand(0), CondRHS = Cond.getOperand(1);
+      ISD::CondCode NewCC = CC;
+      // Else can occur, if the sub arguments are swapped
+      // x < y ? y - x : 0 -> y > x ? y - x : 0
+      if (CC == ISD::SETULE || CC == ISD::SETULT) {
+        std::swap(CondLHS, CondRHS);
+        NewCC = CC == ISD::SETULE ? ISD::SETUGE : ISD::SETUGT;
+      }
+
+      if (CondLHS.getOpcode() == ISD::ZERO_EXTEND &&
+          DAG.isEqualTo(SubRHS, CondRHS) && DAG.isEqualTo(SubLHS, CondLHS)) {
+        SDValue SaturationConst = DAG.getConstant(
+            APInt::getMaxValue(VT.getScalarType().getSizeInBits())
+                .getLimitedValue(),
+            SDLoc(SubRHS), ExtType);
+        SDValue UMin = DAG.getNode(ISD::UMIN, SDLoc(SubRHS), ExtType, SubRHS,
+                                   SaturationConst);
+        Other = DAG.getNode(ISD::SUB, SDLoc(SubXY), VT, CondLHS.getOperand(0),
+                            DAG.getZExtOrTrunc(UMin, SDLoc(SubRHS), VT));
+        Cond = DAG.getNode(NewCC, SDLoc(Cond), VT, Other.getOperand(0),
+                           Other.getOperand(1));
+        CC = NewCC;
+      }
+    }
+
     if (Other.getNode() && Other->getNumOperands() == 2 &&
         DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
       SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
Index: test/CodeGen/X86/psubus.ll
===================================================================
--- test/CodeGen/X86/psubus.ll
+++ test/CodeGen/X86/psubus.ll
@@ -513,3 +513,91 @@
   store <32 x i8> %6, <32 x i8>* %2, align 1
   ret void
 }
+
+define void @test13(i16* nocapture %head, i32* nocapture %w) nounwind {
+; SSE-LABEL: test13:
+; SSE:     psubusw {{%xmm[0-9]}}, {{%xmm[0-9]}}
+;
+; AVX-LABEL: test13:
+; AVX:     vpsubusw {{%xmm[0-9]}}, [[REG1:%xmm[0-9]]], [[REG1]]
+vector.ph:
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
+  %1 = bitcast i16* %0 to <8 x i16>*
+  %2 = load <8 x i16>, <8 x i16>* %1, align 2
+  %3 = getelementptr inbounds i32, i32* %w, i64 0
+  %4 = bitcast i32* %3 to <8 x i32>*
+  %5 = load <8 x i32>, <8 x i32>* %4, align 2
+  %6 = zext <8 x i16> %2 to <8 x i32>
+  %7 = icmp ult <8 x i32> %6, %5
+  %8 = sub <8 x i32> %6, %5
+  %9 = trunc <8 x i32> %8 to <8 x i16>
+  %10 = select <8 x i1> %7, <8 x i16> zeroinitializer, <8 x i16> %9
+  store <8 x i16> %10, <8 x i16>* %1, align 1
+  ret void
+}
+
+define void @test14(i8* nocapture %head, i32* nocapture %w) nounwind {
+; SSE-LABEL: test14:
+; SSE:     psubusb {{%xmm[0-9]}}, {{%xmm[0-9]}}
+;
+; AVX-LABEL: test14:
+; AVX:       vpsubusb {{%xmm[0-9]}}, [[REG1:%xmm[0-9]]], [[REG1]]
+vector.ph:
+  %0 = getelementptr inbounds i8, i8* %head, i64 0
+  %1 = bitcast i8* %0 to <16 x i8>*
+  %2 = load <16 x i8>, <16 x i8>* %1, align 2
+  %3 = getelementptr inbounds i32, i32* %w, i64 0
+  %4 = bitcast i32* %3 to <16 x i32>*
+  %5 = load <16 x i32>, <16 x i32>* %4, align 2
+  %6 = zext <16 x i8> %2 to <16 x i32>
+  %7 = icmp ult <16 x i32> %6, %5
+  %8 = sub <16 x i32> %6, %5
+  %9 = trunc <16 x i32> %8 to <16 x i8>
+  %10 = select <16 x i1> %7, <16 x i8> zeroinitializer, <16 x i8> %9
+  store <16 x i8> %10, <16 x i8>* %1, align 1
+  ret void
+}
+
+define void @test15(i16* nocapture %head, i32* nocapture %w) nounwind {
+; SSE-LABEL: test15:
+; SSE:     psubusw {{%xmm[0-9]}}, {{%xmm[0-9]}}
+;
+; AVX-LABEL: test15:
+; AVX:     vpsubusw {{%xmm[0-9]}}, [[REG1:%xmm[0-9]]], [[REG1]]
+vector.ph:
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
+  %1 = bitcast i16* %0 to <8 x i16>*
+  %2 = load <8 x i16>, <8 x i16>* %1, align 2
+  %3 = getelementptr inbounds i32, i32* %w, i64 0
+  %4 = bitcast i32* %3 to <8 x i32>*
+  %5 = load <8 x i32>, <8 x i32>* %4, align 2
+  %6 = zext <8 x i16> %2 to <8 x i32>
+  %7 = icmp ugt <8 x i32> %6, %5
+  %8 = sub <8 x i32> %6, %5
+  %9 = trunc <8 x i32> %8 to <8 x i16>
+  %10 = select <8 x i1> %7, <8 x i16> %9, <8 x i16> zeroinitializer
+  store <8 x i16> %10, <8 x i16>* %1, align 1
+  ret void
+}
+
+define void @test16(i16* nocapture %head, i32* nocapture %w) nounwind {
+; SSE-LABEL: test16:
+; SSE:     psubusw {{%xmm[0-9]}}, {{%xmm[0-9]}}
+;
+; AVX-LABEL: test16:
+; AVX:     vpsubusw {{%xmm[0-9]}}, [[REG1:%xmm[0-9]]], [[REG1]]
+vector.ph:
+  %0 = getelementptr inbounds i16, i16* %head, i64 0
+  %1 = bitcast i16* %0 to <8 x i16>*
+  %2 = load <8 x i16>, <8 x i16>* %1, align 2
+  %3 = getelementptr inbounds i32, i32* %w, i64 0
+  %4 = bitcast i32* %3 to <8 x i32>*
+  %5 = load <8 x i32>, <8 x i32>* %4, align 2
+  %6 = zext <8 x i16> %2 to <8 x i32>
+  %7 = icmp ult <8 x i32> %5, %6
+  %8 = sub <8 x i32> %6, %5
+  %9 = trunc <8 x i32> %8 to <8 x i16>
+  %10 = select <8 x i1> %7, <8 x i16> %9, <8 x i16> zeroinitializer
+  store <8 x i16> %10, <8 x i16>* %1, align 1
+  ret void
+}